MPC9658 Просмотр технического описания (PDF) - Motorola => Freescale
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MPC9658 Datasheet PDF : 12 Pages
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Freescale Semiconductor, Inc.
MPC9658
Table 6. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit Condition
fref
Input reference frequency
PLL mode, external feedback
÷2 feedbackb
100
÷4 feedbackc
50
250
MHz PLL locked
125
MHz PLL locked
fVCO
fMAX
Input reference frequency in PLL bypass moded
0
VCO lock frequency rangee
200
Output Frequency
÷2 feedbackc
100
÷4 feedbackd
50
250
MHz
500
MHz
250
MHz PLL locked
125
MHz PLL locked
VPP
VCMRf
tPW,MIN
t(∅)
Peak-to-peak input voltage (PCLK)
Common Mode Range (PCLK)
Input Reference Pulse Widthg
Propagation Delay (static phase offset)
PCLK to FB_IN
fREF=100 MHz
any frequency
500
1.2
2.0
–70
–125
1000
mV LVPECL
VCC-0.9
V
LVPECL
ns
+80
+125
PLL locked
ps
ps
tPD
tsk(O)
DC
Propagation Delay (PLL and divider bypass) PCLK to Q0-9
1.0
4.0
ns
Output-to-output Skewh
120
ps
Output Duty Cyclei
(T÷2)–400 T÷2 (T÷2)+400 ps
tr, tf
Output Rise/Fall Time
0.1
tPLZ, HZ Output Disable Time
tPZL, LZ Output Enable Time
tJIT(CC) Cycle-to-cycle jitter
tJIT(PER)
tJIT(∅)
Period Jitter
I/O Phase Jitter fVCO=500 MHz and ÷ 2 feedback, RMS (1σ)j
fVCO=500 MHz and ÷ 4 feedback, RMS (1σ)
BW
PLL closed loop bandwidthk
÷ 2 feedbackc
÷ 4 feedbackd
6–20
2–8
1.0
ns 0.55 to 2.4V
7.0
ns
6.0
ns
80
ps
80
ps
5.5
ps
6.5
ps
MHz
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a AC characteristics apply for parallel output termination of 50Ω to VTT.
b ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
c ÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
d In bypass mode, the MPC9658 divides the input reference clock.
e The input frequency fref must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
f VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅).
g Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF,MIN.
h See application section for part-to-part skew calculation in PLL zero-delay mode.
i Output duty cycle is DC = (0.5 ± 400 ps ⋅ fOUT) ⋅ 100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period.
j See application section for a jitter calculation for other confidence factors than 1 s and a characteristic for other VCO frequencies.
k -3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
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