MPC9658
Freescale Semiconductor, Inc.
Q0
VCC
Q1
2⋅25k
0
PCLK
PCLK
0
÷1
0
Q2
÷2
1
& Ref
VCO
1
÷2
1
Q3
PLL
Q4
200–500 MHz
VCC
Q5
25k
Q6
FB_IN
FB
VCC
Q7
3⋅25k
Q8
PLL_EN
Q9
VCO_SEL
BYPASS
QFB
MR/OE
25k
Figure 1. MPC9658 Logic Diagram
24 23 22 21 20 19 18 17
GND
25
16
Q6
Q1
26
15
VCC
VCC
27
14
Q7
Q0
28
GND
29
MPC9658
13
GND
12
Q8
QFB
30
11
VCC
VCC
31
10
Q9
VCO_SEL
32
9
GND
12345678
Figure 2. MPC9658 32–Lead Package Pinout (Top View)
MOTOROLA
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TIMING SOLUTIONS