IDT72T4098 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72T4098

2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION

Integrated Device Technology 

IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT

CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol &

Pin No.

WSDR(1)

(L1)

Name

Write Single Data

Rate

I/O TYPE

LVTTL

INPUT

Description

When LOW, this input pin sets the write port to Single Data Clock mode. When HIGH, the write port will

operate in Double Data Clock mode. This pin must be tied either HIGH or LOW and cannot toggle

during operation.

VCC

+2.5V Supply

(See below)

INPUT There are Vcc supply inputs and must be connected to the 2.5V supply rail.

VDDQ

O/P Rail Voltage

(See below)

INPUT

This pin should be tied to the desired voltage rail for providing power to the output drivers. Nominally 1.5V

or 1.8V for HSTL, 2.5V for LVTTL.

GND

Core Ground Pin INPUT

(See below)

These are Ground pins are for the core device and must be connected to the GND rail.

Vref

Reference

INPUT This is a Voltage Reference input and must be connected to a voltage level determined in the

(T3)

Voltage

Recommended DC Operating Conditions section. This provides the reference voltage when using HSTL

class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to pages 25-28 and Figures 5-7.

PIN NUMBER TABLE

Symbol

Name

I/O TYPE

Pin Number

D0-39

DataInputs HSTL-LVTTL D0-C3, D1-A4, D2-B4, D3-C4, D4-A5, D5-B5, D6-C5, D7-A6, D8-B6, D9-A7, D10-R7, D11-T7,

INPUT D12-R6, D13-T6, D14-R5, D15-T5, D16-R4, D17-T4, D18-P3, D19-R3, D20-N2, D21-P2, D22-R2,

D23-N1, D24-P1, D25-R1, D26-N3, D(27-29)-M(1-3), D30-E1, D(31-33)-D(3-1), D34-C1,

D(35,36)-B(1,2), D37-C2, D38-A3, D39-B3

Q0-39

DataOutputs HSTL-LVTTL Q0-B10, Q1-A10, Q2-B11, Q3-A11, Q4-B12, Q5-A12, Q6-B13, Q7-A13, Q8-B14, Q9-A14, Q10-T14

OUTPUT Q11-R14, Q12-T13, Q13-R13, Q14-T12, Q15-R12, Q16-T11, Q17-R11, Q18-T10, Q19-R10,

Q(20,21)-C(14,15), Q(22,23)-B(15,16), Q24-C16, Q(25-27)-D(16-14), Q(28,29)-E(16,15),

Q(30,31)-M(15,16), Q(32-34)- N(14-16), Q(35-37)-P(14-16), Q(38,39)-R(15,16)

VCC

+2.5V Supply

INPUT A(1,2), C(6,7), D(4-7), K4, L4, M4, N(4-7), P(5-7), T(1,2)

VDDQ

O/P Rail Voltage INPUT A(15,16), C(10-13), D(10-13), E13, F(4,13), G(4,14), H(4,14), J14, K14, L14, M13, N(10-13),

P(10-13), T(15,16)

GND

Ground Pin

INPUT A(8,9), B(8,9), C(8,9), D(8,9), E4, G(7-10,13), H(7-10,13), J(4,7-10,13), K(7-10,13), L13, N(8,9),

P(4,8,9), R(8,9), T(8,9)

8

SEPTEMBER 21, 2004

Share Link: