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IDT72T4098

2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION

Integrated Device Technology 

IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT

CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION

Symbol &

Pin No.

BM(1)

(K2)

Name

Bus-Matching

I/O TYPE

Description

LVTTL During Master Reset, this pin along with IW and OW selects the bus sizes for both write and read

INPUT ports.

D0-D39

Data Inputs

(See Pin No.

table for details)

HSTL-LVTTL Data inputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused input pins are in a don’t

INPUT care state. The data bus is sampled on both rising and falling edges of WCLK whenWEN is enabled and

DDR Mode is enabled or on the rising edges of WCLK only in SDR Mode.

EF/OR

(M14)

Empty Flag/

Output Ready

HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory

OUTPUT is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data

available at the outputs.

ERCLK

(L16)

Echo Read

Clock

HSTL-LVTTL Read Clock Echo output, must be equal to or faster than the Qn data outputs.

OUTPUT

EREN

(K16)

Echo Read

Enable

HSTL-LVTTL Read Enable Echo output, used in conjunction with ERCLK.

OUTPUT

FF/IR

(H3)

Full Flag/

Input Ready

HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is

OUTPUT empty. In FWFT mode, the IR function is selected. IR indicates whether or not there is space available

for writing to the FIFO memory.

FSEL0(1)

(J3)

Flag Select Bit 0

LVTTL DuringMasterReset,thisinputalongwithFSEL1willselectthedefaultoffsetvaluesfortheprogrammable

INPUT flags PAE and PAF. There are four possible settings available.

FSEL1(1)

(J2)

Flag Select Bit 1

LVTTL During Master Reset, this input along with FSEL0 will select the default offset values for the programmable

INPUT flags PAE and PAF. There are four possible settings available.

FWFT

(G2)

First Word Fall

Through

LVTTL During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in

INPUT DDR mode. In SDR mode, the first word will always fall through on the rising edge.

HSTL(1)

(B7)

HSTL Select

LVTTL This input pin is used to select HSTL or 2.5V LVTTL device operation. If HSTL inputs are required, this

INPUT input must be tied HIGH, otherwise it must be tied LOW and cannot toggle during operation.

IW(1)

Input Width

LVTTL During Master Reset, this pin along with OW and BM, selects the bus width of the read and write port.

(K1)

INPUT

MARK

(E14)

Mark Read

Pointer for

Retransmit

HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit

INPUT operation will reset the read pointer to this position. There is an unlimited number to times to set the mark

location, but only the most recent location marked will be acknowledged.

MRS

MasterReset HSTL-LVTTL MRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros.DuringMaster

(J1)

INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, and

programmable flag default settings.

OE

(G15)

OutputEnable HSTL-LVTTL WhenHIGH,dataoutputsQ0-Q39areinhighimpedance.WhenLOW,thedataoutputsQ0-Q39areenabled.

INPUT No other outputs are affected by OE.

OW(1)

Output Width

LVTTL During Master Reset, this pin along with IW and BM, selects the bus width of the read and write port.

(L3)

INPUT

PAE

Programmable HSTL-LVTTL PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n, which is

(L15)

Almost-Empty

OUTPUT storedintheEmptyOffsetregister.PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthan

Flag

offset n.

PAF

Programmable HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored

(G3)

Almost-FullFlag OUTPUT in the Full Offset register. PAFgoes LOW if the number of free locations in the FIFO memory is less than

or equal to m.

PRS

PartialReset HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output registers to all zeros. During Partial

(K3)

INPUT Reset, the existing mode (IDT standard or FWFT) and programmable flag settings are not affected.

Q0-Q39

Data Outputs

(See Pin No.

table for details)

HSTL-LVTTL Data outputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused output pins should not

OUTPUT be connected. The output data is clocked on both rising and falling edges of RCLK whenREN is enabled

and DDR Mode is enabled or on the rising edges of RCLK only in SDR Mode.

RCLK

(G16)

Read Clock

HSTL-LVTTL InputclockwhenusedinconjunctionwithRENforreadingdatafromtheFIFOmemoryandoutputregister.

INPUT

6

SEPTEMBER 21, 2004

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