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IDT72T4098

2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION

Integrated Device Technology 

IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT

CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

PAE and PAF flags can be programmed independently to switch at any point

in memory. Programmable offsets mark the location within the internal memory

that activates the PAE and PAF flags and can only be programmed serially. To

program the offsets, set SEN active and data can be loaded via the Serial Input

(SI) pin at the rising edge of SCLK. To read out the offset registers serially, set

SREN active and data can be read out via the Serial Output (SO) pin at the rising

edge of SCLK. Four default offset settings are also provided, so that PAE can

be marked at a predefined number of locations from the empty boundary and

the PAF threshold can also be marked at similar predefined values from the full

boundary. The default offset values are set during Master Reset by the state

of the FSEL0 and FSEL1 pins.

During Master Reset (MRS), the following events occur: the read and write

pointers are set to the first location of the internal FIFO memory, the FWFT pin

selects IDT Standard mode or FWFT mode, the bus width configuration of the

read and write port is determined by the state of IW and OW, and the default offset

values for the programmable flags are set.

The Partial Reset (PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode and the values stored in the

programmable offset registers before Partial Reset remain unchanged. The

flags are updated according to the timing mode and offsets in effect. PRS is useful

for resetting a device in mid-operation, when reprogramming programmable

flags would be undesirable.

The timing of the PAE and PAF flags are synchronous to RCLK and WCLK,

respectively. The PAE flag is asserted upon the rising edge of RCLK only and

not WCLK. Similarly the PAF is asserted and updated on the rising edge of

WCLK only and not RCLK.

This device includes a Retransmit from Mark feature that utilizes two control

inputs, MARK and RT (Retransmit). If the MARK input is enabled with respect

to the RCLK, the memory location being read at the point will be marked. Any

subsequent retransmit operation (when RT goes LOW), will reset the read

pointer to this “marked” location.

The device can be configured with different input and output bus widths as

previously stated. These rates are: x40 to x40, x40 to x20,x40 to x10, x20 to

x40, and x10 to x40.

If, at any time, the FIFO is not actively performing an operation, the chip will

automatically power down. Once in the power down state, the standby supply

current consumption is minimized. Initiating any operation (by activating control

inputs) will immediately take the device out of the power down state.

A JTAG test port is provided, here the FIFO has fully functional boundary

Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and

Boundary Scan Architecture.

The Double Data Rate FIFO has the capability of operating in either LVTTL

or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both

input and output ports will operate in either HSTL or LVTTL mode, but cannot

be selected independent of one another.

The IDT72T4088/72T4098/72T40108/72T40118 are fabricated using

IDT’s high-speed submicron CMOS technology.

4

SEPTEMBER 21, 2004

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