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IDT72T4098

2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION

Integrated Device Technology 

IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT

CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Symbol &

Pin No.

RCS

(F14)

REN

(F16)

RSDR(1)

(L2)

Name

I/O TYPE

Description

Read Chip Select HSTL-LVTTL RCS provides synchronous enable/disable control of the read port and High-Impedance control of the

INPUT Qn data outputs, synchronous to RCLK. When using RCS the OE pin must be tied LOW. During Master

or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance

regardless of RCS.

Read Enable

HSTL-LVTTL When LOW and in DDR mode, REN along with a rising and falling edge of RCLK will send data in FIFO

INPUT memory to the output register and read the current data in output register. In SDR mode data will only be

read on the rising edge of RCLK only.

Read Single Data LVTTL WhenLOW,thisinputpinsetsthereadporttoSingleDataClockmode.WhenHIGH,thereadportwilloperate

Rate

INPUT inDoubleDataClockmode.ThispinmustbetiedeitherHIGHorLOWandcannottoggleduringoperation.

RT

(F15)

Retransmit

HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the read pointer to the first location in memory. EF flag

INPUT is set to LOW (OR to HIGH in FWFT mode). The write pointer, offset registers, and flag settings are not

affected. If a mark has been set via the MARK input pin, then the read pointer will initialize to the mark location

when RT is asserted.

SCLK

(H15)

SEN

(J15)

Serial Clock

Serial Input

Enable

LVTTL

INPUT

A rising edge of SCLK will clock the serial data present on the SI input into the offset registers provided

that SEN is enabled. A rising edge of SCLK will also read data out of the offset registers provided that SREN

is enabled.

HSTL-LVTTL SEN used in conjunction with SI and SCLK enables serial loading of the programmable flag offsets.

INPUT

SREN

(J16)

SI

(H16)

SO

(K15)

Serial Read

Enable

Serial Input

Serial Output

HSTL-LVTTL SREN used in conjunction with SO and SCLK enables serial reading of the programmable flag offsets.

INPUT

HSTL-LVTTL Thisinputpinisusedtoloadserialdataintotheprogrammableflagoffsets.UsedinconjunctionwithSEN

INPUT and SCLK.

HSTL-LVTTL This output pin is used to read data from the programmable flag offsets. Used in conjunction with SREN

OUTPUT and SCLK.

TCK(2)

(F1)

JTAG Clock

HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test

INPUT operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge

of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs

to be tied to GND.

TDI(2)

JTAG Test Data HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,

(E2)

Input

INPUT testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister

and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

TDO(2)

(F3)

JTAG Test Data

Output

HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,

OUTPUT testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,

ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-

DR and SHIFT-IR controller states.

TMS(2)

(F2)

JTAG Mode

Select

HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the

INPUT thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.

TRST(2)

(E3)

WCLK

(G1)

WCS

(H2)

WEN

(H1)

JTAGReset HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not

INPUT automaticallyresetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHfor

five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-

impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied

with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be

tied to GND. An internal pull-up resistor forces TRST HIGH if left unconnected.

Write Clock

HSTL-LVTTL Input clock when used in conjunction with WEN for writing data into the FIFO memory.

INPUT

WriteChipSelect HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.

INPUT

Write Enable

HSTL-LVTTL When LOW and in DDR mode, WEN along with a rising and falling edge of WCLK will write data into the

INPUT FIFO memory. In SDR mode data will only be read on the rising edge of RCLK only.

7

SEPTEMBER 21, 2004

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