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IDT72T4098

2.5 VOLT HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION

Integrated Device Technology

IDT72T4098 Datasheet PDF : 52 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT

CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)

Commercial

IDT72T4088L4

IDT72T4098L4

IDT72T40108L4

IDT72T40118L4

IDT72T4088L5

IDT72T4098L5

IDT72T40108L5

IDT72T40118L5

Symbol

Parameter

Min. Max. Min. Max.

fS1

Clock Cycle Frequency SDR

—

250

—

200

fS2

Clock Cycle Frequency DDR

—

110

—

100

Data Access Time

0.6

3.2

0.6

3.6

tASO Data Access Serial Output Time

0.6

3.2

0.6

3.6

tCLK1 Clock Cycle Time SDR

—

tCLK2 Clock Cycle Time DDR

9.1

—

tCLKH1 Clock High Time SDR

1.8

—

2.3

—

tCLKH2 Clock High Time DDR

4.0

—

4.5

—

tCLKL1 Clock Low Time SDR

1.8

—

2.3

—

tCLKL2 Clock Low Time DDR

4.0

—

4.5

—

tDS

Data Setup Time

1.2

—

1.5

—

tDH

Data Hold Time

0.5

—

0.5

—

tENS

Enable Setup Time

1.2

—

1.5

—

tENH

tWCSS

tWCSH

Enable Hold Time

WCS setup time

WCS hold time

0.5

—

0.5

—

1.2

—

1.5

—

0.5

—

0.5

—

Clock Cycle Frequency (SCLK)

—

tSCLK Serial Clock Cycle

100

—

100

—

tSCKH Serial Clock High

—

tSCKL Serial Clock Low

—

tSDS

Serial Data In Setup

—

tSDH

Serial Data In Hold

—

tSENS Serial Enable Setup

—

tSENH Serial Enable Hold

—

tRS

Reset Pulse Width(3)

—

tRSS

Reset Setup Time

—

tHRSS HSTL Reset Setup Time

—

tRSR

Reset Recovery Time

—

tRSF

Reset to Flag and Output Time

—

tOLZ

Output Enable to Output in Low Z(4)

—

tOE

Output Enable to Output Valid

—

3.2

—

3.6

tOHZ

Output Enable to Output in High Z(4)

tWFF

Write Clock to FF or IR

tREF

Read Clock to EF or OR

—

3.2

—

3.6

—

3.2

—

3.6

—

3.2

—

3.6

tPAFS Write Clock to Programmable Almost-Full Flag

—

3.2

—

3.6

tPAES Read Clock to Programmable Almost-EmptyFlag

—

3.2

—

3.6

tERCLK

tCLKEN

RCLK to Echo RCLK output

RCLK to Echo REN output

—

3.6

—

3.2

—

3.6

tRCSLZ RCLK to Active from High-Z

—

3.2

—

3.6

tRCSHZ RCLK to High-Z(4)

—

3.2

—

3.6

tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR

3.5

—

tSKEW2

tSKEW3

Skew time between RCLK & WCLK for EF/OR & FF/IR in DDR mode

Skew time between RCLK and WCLK for PAE and PAF

3.5

—

Com’l & Ind’l(2)

IDT72T4088L6-7

IDT72T4098L6-7

IDT72T40108L6-7

IDT72T40118L6-7

Min. Max.

—

150

—

0.6

3.8

0.6

3.8

6.7

—

2.8

—

6.0

—

2.8

—

6.0

—

2.0

—

0.5

—

2.0

—

0.5

—

2.0

—

0.5

—

100

—

3.8

—

3.8

—

3.8

—

3.8

—

3.8

—

3.8

—

4.3

—

3.8

—

3.8

—

3.8

—

Commercial

IDT72T4088L10

IDT72T4098L10

IDT72T40108L10

IDT72T40118L10

Min. Max.

— 100

— 50

0.6 4.5

10 —

20 —

4.5 —

9.5 —

4.5 —

9.5 —

3.0 —

0.5 —

3.0 —

0.5 —

3.0 —

0.5 —

— 10

100 —

45 —

15 —

—

30 —

15 —

—

10 —

— 15

—

— 4.5

—

— 4.5

—

Unit

MHz

µs

NOTES:

1. All AC timings apply to both IDT Standard mode and First Word Fall Through mode.

2. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades are available by special order.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

SEPTEMBER 21, 2004

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