ADM4850 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
Список матч
ADM4850 Datasheet PDF : 16 Pages
| |||
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
Skew, tSKEW
Rise/Fall Times, tR, tF
Enable Time, tZH
Disable Time, tZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
Min
Typ
Max
Unit
Test Conditions/Comments
2.5
Mbps
50
180
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
50
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
140
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
180
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
180
ns
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4852
4000
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
55
190
ns
CL = 15 pF, see Figure 22
50
ns
CL = 15 pF, see Figure 22
5
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
20
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
4000
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
50
330
3000 ns
ADM48521
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay, tPLH, tPHL
Skew, tSKEW
Rise/Fall Times, tR, tF
Enable Time, tZH
Disable Time, tZL
Enable Time from Shutdown
RECEIVER
Propagation Delay, tPLH, tPHL
Differential Skew, tSKEW
Enable Time
Disable Time
Enable Time from Shutdown
Time to Shutdown
Min
Typ
Max
Unit
Test Conditions/Comments
10
Mbps
0
30
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
10
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
30
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
35
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
35
ns
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4853
4000
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
55
190
ns
CL = 15 pF, see Figure 22
30
ns
CL = 15 pF, see Figure 22
5
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
20
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
4000
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
50
330
3000 ns
ADM48531
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. D | Page 5 of 16
Share Link: 