GD25Q20 Просмотр технического описания (PDF) - Unspecified

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GD25Q20

GD25Q20BxIGx Uniform sector dual and quad serial flash

Unspecified 

SO(IO1)

51515151

5151 5

WP#(IO2)

62626262

6262 6

GD2H5OLQD#2(IO03)BxIG7 x3 U7n3ifo7rm3 s7ec3 tor dual an7 d3 q7ua3d s7 erial flash

A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2

7.11. Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest

address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure14. The first

byte addressed can be at any location. The address is automatically incremented to the next higher address after each

byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word

Fast read command. To ensure optimum performance the High Performance Mode (HPM) command (A3h) must be

executed once, prior to the Quad I/O Word Fast Read command.

Quad I/O WordUFnasiftoRremadSWeicthto“Crontinuous Read Mode”

The Quad I/ODWuoardl Faanst dReQaducoamdmaSned rciaan lfuFrthlaersrehduce command overhead througGh Dset2tin5gQth4e 0“CBon/t2in0uoBus

Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M7-0) =AXH, then the

next Quad I/O Word Fast Read command (after CS# is raise2d4and then lowered) does not require the E7H command code.

The command sequence is shown in followed Figure15. If the “Continuous Read Mode” bits (M7-0) are any value other

than AXH, the next command requires the first E7H command code, thus returning to normal operation. A “Continuous

Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.

Figure 14. Quad I/O Word Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SI(IO0)

SO(IO1)

Command

E7H

40404040

51515151

404040 4

515151 5

WP#(IO2)

62626262

626262 6

HOLD#(IO3)

73737373

737373 7

A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

Figure 15. Quad I/O Word Fast Read Sequence Diagram (M7-0= AXH)

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SI(IO0)

40404040

404040 4

SO(IO1)

51515151

515151 5

WP#(IO2)

62626262

626262 6

HOLD#(IO3)

73737373

737373 7

A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3

7.12. Page Program (PP) (02H)

The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must

previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.

bytes

The

and

Page Program (PP) command

at least one data byte on SI. If

itsheen8telereadstbsyigdnr3iifvi8cinagn- tC2aS0d#drLeossw,biftosllo(Aw7e-dA0b)yatrheencootmamll zaenrdo,caoldl etr,atnhsremeittaedddRdreeastvas.1.1

that goes beyond the end of the current page are programmed from the start address of the same page (from the address

whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence. The

Page Program command sequence: CS# goes low � sending Page Program command � 3-byte address on SI � at least

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