GD25Q20 Просмотр технического описания (PDF) - Unspecified

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GD25Q20

GD25Q20BxIGx Uniform sector dual and quad serial flash

Unspecified 

GD2U5nQif2or0mBSxeIcGtoxr Uniform sector dual and quad serial flash

Dual and Quad Serial Flash

GD25Q40B/20B

7.6. Read Data Bytes At Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte

address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,

at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The

first byte addressed can be at any location. The address is automatically incremented to the next higher address after each

byte of data is shifted out.

Figure 7. Read Data Bytes at Higher Speed Sequence Diagram

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 10

28 29 30 31

SI

SO

CS#

SCLK

SI

SO

Command

0BH

High-Z

24-bit address

23 22 21

3210

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Byte

76543210

Data Out1

Data Out2

76543210765

MSB

MSB

7.7. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being

latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.

The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out.

Figure 8 Dual Output Fast Read Sequence Diagram

CS#

SCLK

0 1 2 3 4 5 6 7 8 9 10

28 29 30 31

SI

SO

CS#

SCLK

SI

SO

Command

3BH

High-Z

24-bit address

23 22 21

3210

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Clocks

642064206

Data Out1 Data Out2

75317531 7

MSB

MSB

21

38 - 16

Rev.1.1

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