GD25Q20 Просмотр технического описания (PDF) - Unspecified
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GD25Q20 Datasheet PDF : 38 Pages
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SO(IO1)
51515151
515151 5
WP#(IO2)
62626262
626262 6
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A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
7.12. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address
bytes and at least oUnendiafotarbmyte SoneScI.tIof trhe 8 least significant address bits (A7-A0) are not all zero, all transmitted data
that goes beyond thDe uenadlofathnedcuQrreuntapadgeSaererpiraoglraFmlmaesdhfrom the start address of the samGe Dpa2ge5(Qfro4m0thBe a/2dd0reBss
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unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0)
25
is not executed.
Figure 16. Page Program Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SI
CS#
SCLK
Command
02H
24-bit address
Data Byte 1
23 22 21
321076543210
MSB
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
SI
7654321076543210
76543210
MSB
MSB
MSB
7.13. Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the chosen sector. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered
by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid
address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence.
The Sector Erase command sequence: CS# goes low � sending Sector Erase command � 3-byte address on SI �
CS# goes high. The command sequence is shown in Figure17. CS# must be driven high after the eighth bit of the last
address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven
high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected
by the Block Protect (BP4, BP3, BP2, BP1, BP0) bit (see Table1.) is not executed.
Figure 17. Sector Erase Sequence Diagram
CS#
SCLK
SI
0123456789
38 - 21
29 30 31
Command
20H
24 Bits Address
23 22
210
MSB
Rev.1.1
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