GD25Q20 Просмотр технического описания (PDF) - Unspecified
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GD25Q20 Datasheet PDF : 38 Pages
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Uniform Sector
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7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table2. Commands
Command Name
Write Enable
Write Disable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Quad I/O
Fast Read
Quad I/O Word
Fast Read(7)
Continuous Read Reset
Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
Program/Erase
Suspend
Program/Erase Resume
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
Byte 1
06H
04H
05H
35H
01H
03H
0BH
3BH
BBH
6BH
EBH
E7H
FFH
02H
20H
52H
D8H
C7/60H
75H
7AH
B9H
ABH
ABH
Byte 2
Byte 3
Byte 4
Byte 5
(S7-S0)
(S15-S8)
(S7-S0)
A23-A16
A23-A16
A23-A16
(S15-S8)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
A23-A8(2)
A23-A16
A7-A0
M7-M0(2)
A15-A8
(D7-D0)(1)
A7-A0
dummy
A23-A0
M7-M0(4)
A23-A0
M7-M0(4)
dummy(5)
dummy(6)
(D7-D0)(3)
(D7-D0)(3)
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
dummy
dummy
dummy
(DID7-
DID0)
Byte 6
n-Bytes
(continuous)
(continuous)
(Next byte)
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
(continuous)
(continuous)
(D7-D0)(3) (continuous)
(continuous)
(continuous)
Next byte
(continuous)
16
38 - 12
Rev.1.1
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