W199 Просмотр технического описания (PDF) - Cypress Semiconductor
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W199 Datasheet PDF : 14 Pages
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PRELIMINARY
W199
Spread Spectrum FTG for VIA Apollo Pro-133
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single-chip system frequency synthesizer for VIA
Apollo Pro-133
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• 13 SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
• Available in 48-pin SSOP
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin 2
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
FS3 FS2 FS1 FS0 CPU1 (MHz)
1
1
1
1
133.3
1
1
1
0
124
1
1
0
1
150
1
1
0
0
140
1
0
1
1
105
1
0
1
0
110
1
0
0
1
115
1
0
0
0
120
0
1
1
1
100
0
1
1
0
133.3
0
1
0
1
112
0
1
0
0
103
0
0
1
1
66.8
0
0
1
0
83.3
0
0
0
1
75
0
0
0
0
124
PCI_F, 1:5
(MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Logic Block Diagram
X1
XTAL
X2
OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I2C
Logic
PLL2
Stop
Clock
Control
÷2
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
Pin Configuration[1]
VDDQ3 1
REF0/(PCI_STOP#) 2
GND 3
X1 4
X2 5
VDDQ3 6
PCI_F/MODE 7
PCI1/FS3 8
GND 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
VDDQ3 14
SDRAMIN 15
GND 16
SDRAM11 17
SDRAM10 18
VDDQ3 19
SDRAM9 20
SDRAM8 21
GND
{ I2C SDATA
22
23
SCLK 24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 CLK_STOP#
40 SDRAM_F
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
SDRAMIN
Stop
Clock
Control
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
I2C is a trademark of Philips Corporation.
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 19, 1999, rev. **
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