M65762FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M65762FP

QM-CODER

MITSUBISHI ELECTRIC  

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

(3) Command Register (W)

(Address: 2)

d7

d3

d0

CMD_REG:

0 JP RC JC IC

d0 (IC) :Context table RAM initialization start command (1: Start

initialization)

Setting this bit to 1 starts to initialize context table RAM.

When the initialization is completed automatically returns

this bit to 0.

d1 (JC) : P r o c e s s i n g (coding/decoding/through) start/end

command (1: Start of processing, 0: End of processing)

Setting this bit to 1 starts processing (coding/decoding,

image data through and lead/store of line memory).

Before the issuance of this command, concrete

operation mode must be set in the operation mode setup

register.

When the processing for the number of setup lines ends

with the end of termination selected this bit automatically

returns to 0.

(Note)When this JC bit is set to 0 during the coding

process (is in progress,) and input of image data

is stopped, the coding is stopped (flashed) even if

the set lines are not filled. When this bit is set to 0

auring decoding process, and input of encoding

data ceases, processing for the number of setup

lines is carried out assuming coding data "00" to

have been input. In the case of multi-stripe

coding, however, process must not be stopped by

setting this bit to 0 except for the final stripe.

d2 (RC) :Load/store start/end command of context table RAM (1:

Start of load/store, 0: End of load/store)

Setting this bit to 1 can load context data into context

table RAM from outside via a buffer register or can store

context data in outside. (See the section for buffer

register.)

When load/store processing is completed, this bit must

be set to 0.

d3 (JP) : T e m p o r a r y s t o p m o d e o f p r o c e s s i n g ( c o d i n g /

decoding/through)/termination end mode selection

(1: Selection of temporary stop, 0: Selection of

terminationend) Issuance of processing start command

d1 (JC) with this JP bit set to 1 temporarily stops

performing the process operation at the completion of

processing for the number of setup lines. After that,

reissuance of processing start command d1 (JC)

restarts processing. (See Section 4.(3).)

(4) Status register (R)

(Address: 2)

d7

d5

d0

STAT_REG :

0 PS SC IS MS DS JS

d0 (JS)

: P r o c e s s i n g (initialization/coding/decoding/through)

status (0: Processing in progress (temporary stop or

initial), 1: Completion of processing)

This JS bit is set to 1 in the following cases: when the

initialization is complete with the RAM initialization

command issued (IC = 1), when all coding data is read

completely at time of coding with the start command of

termination end processing issued (JC=1, JP=0), and

when all image data is read completely at time of image

data through and at time of decoding. When the

temporary stop processing start command is issued (JC

= 1, JP = 1), this JS bit remains to be 0, even if the

process for the number of setup lines ends. (However,

an interruption occurs at time of temporary stop.)

When this bit is set to 1, data can be read/written on the

code data bus. (This bit is equivalent to the CDRQ pin.)

d2 (MS) :Detects marker code at time of decoding (0: Not

detected, 1: Detected)

This bit is set to 1 when some marker code is detected at

time of decoding.

d3 (IS) :Status of interrupt request (INTR pin) (0: Not requested,

1: Requested)

d4 (SC) :SC count-over error at time of coding (0: Normal, 1:

Occurrence of SC counter overflow)

(Note)The SC counter is a counter for consecutive "FF"

data bytes generated in the coding process.

Though coding process continues if the SC

counter overflows, normal coding data is not

output (encoding error).

d5 (PS) :Processing (temporary stop/termination end) mode (1:

Temporary stop processing mode, 0: Termination end

processing mode)

This PS bit corresponds to the selection of process

temporary stop/termination end of the d3 (JP) bit of

command register.

(5) Interrupt enable register (W/R)

(Address: 3)

d7

d3

d0

IENB_REG: MP

0

SE ME DE JE

d0 (JE) : P r o c e s s i n g (initialization/coding/decoding/through)

Temporary stop/termination end interrupt (0: Interrupt

mask, 1: Interrupt enable)

d1 (DE) :Coding data (image data) read/write ready interrupt (0:

Interrupt mask, 1: Interrupt enable)

d2 (ME) :Marker code detection interrupt at time of decoding (0:

Interrupt mask, 1: Interrupt enable)

d3 (SE) :SC count-over error interrupt at time of coding (0:

Interrupt mask, 1: Interrupt enable)

(Note)Bits d0 to d3 are interrupt enable of bits d0 to d2

and d4 corresponding to the status register.

When one of the status bits set to interrupt enable

is set to 1, the interrupt request signal (INTR) is

asserted (for d0 (JE), an interrupt occurs even at

the time of temporary stop).

When the status is set to 0 by H/W reset etc., or

when interrupt factor is eliminated by interruption

masking, INTR is negated. The status register is

not cleared by occurrence of interruption or by

R/W of interruption enable register.

d7 (MP) :Indication of pause at time of marker code detection (0:

Indication of continuation/restart, 1: Indication of

temporary pause)

If this MP bit is in advance set to 1 in decoding, the

decoding temporarily pauses at the time of marker code

detected.

(When the ME bit is set to 1, an interruption occurs when

marker code is detected.)

When decoding process is not completed at time of

temporary pause of marker detection, the register for

setting the number of lines can be respecified (See Item

(7).) Afterwards, setting this MP bit to 0 restarts the

decoding process (the decoding process is carried out

for the number of set lines).

d1 (DS) :Ready for reading/writing coding data (image data case

of the through mode) on the code data bus (1: Ready, 0:

Read/write disabled)

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