M65762FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M65762FP

QM-CODER

MITSUBISHI ELECTRIC  

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

(6) Register for setting the number of pixels (W/R)

d7

d0

(Address: 4) PEL_REG_L:

PEL_L

(Address: 5) PEL_REG_H: 0

PEL_H

d7

d5

d0

d0-7 (PEL_L) :Sets the number of pixels in a line. (Low byte)

d0-5 (PEL_H) :Sets the number of pixels in a line. (Upper byte)

A maximum of 8192 pixels can be set at the 3-line

template. A maximum of 10240 pixels can be set

at the 2-line template.

Set the number of pixels to be actually coded

(decoded) at time of scale-up (scale-down).

When the image data bus is 16-bits (32-bits) with

the parallel I/F selected, set the number of pixels to

multiples of 16 (multiples of 32).

With the serial I/F selected, set the number of

pixels to multiples of 8.

(7) Register for setting the number of lines (W/R)

d7

d0

(Address: 6) LSET_REG_L:

LSET_L

(Address: 7) LSET_REG_H:

LSET_H

d0-7 (LSET_L) :Sets the number of lines to be processed. (Low

order byte) (1 to 65535: 0 line is not allowed.)

d0-7 (LSET_H) :Sets the number of lines to be processed. (High

order byte)

At time of scale-down (scale-up), set the number of

lines to be actually coded (decoded).

Set the number of lines (number of relative lines)

ranging from the processing start command to be

issued next to the temporary stop/termination end

just after. This register must be set to a specific

value before the issuance of the process start

command.

As far as the following conditions are satisfied, this

register can be rewritten in the course of

processing.

•When the maximum value (65535) is set before

issuance of the processing start command, an

arbitrary value can be set once in the course of

processing.

•When a value except for the maximum value

(65535) is set before issuance of the processing

start command, and the value requires to be

respecified in the course, respecify the maximum

value (65535) once and then respecify a desired

value.

87 6

543 29

10?

3-line template

8543 2 9

7610 ?

2-line template

Figure 4. Address Assignment of Context Table RAM

(Number for address bit (LSB: 0, MSB: 9), MSB: 9 for AT pixel)

(8) Processing line count register (R)

d7

d0

(Address: 8) LIN_REG_L:

LINE_L

(Address: 9) LIN_REG_H:

LINE_H

d0-7 (LINE_L) :Read out the number of lines actually processed

(low byte) (0 to 65535)

d0-7 (LINE_H) :Read out the number of lines actually processed

(upper byte)

The number of processed lines ≥ number of set

lines, coding/decoding/through processing stop

temporary/end of processing.

(Note)The number of lines in this process is cleared

to 0 with the processing start command issued.

(9) Buffer register (W/R)

d7

d0

(Address: A) DWR_BUF:

DWR

d0-7 (DWR)

:Data for loading/storing context table RAM

This register is a buffer for loading data into t h e

context table RAM via the host bus or for storing

data outside. After issuance of load/store start

command of the context table RAM (command

register d3 = 1), this register is available to start

loading or storing data. Prediction value (MPS) and

prediction unmatched probability (LSZ) can be

stored in context table RAM for a unit of 1024

contexts in total. Figure 4 and Table 4 provide the

address assignment of context table RAM and the

data bit array.

Since context table RAM is 2-byte data, access is

gained alternately in order from low byte to upper

byte. Each time two-byte access is gained, the

RAM address is automatically incremented

(sequential access from address 0).

(Note1)Data is not allowed to be loaded and stored

at a time. Random access to RAM is not

allowed.

(Note2)Only 133 types specified by the JBIG

international standard (See attached Figure

A.2) are allowed to be specified for the LSZ

value.

(For example, load '5a1d' for initialization.)

Table 4. Data Bit Array of Context Table RAM

High order byte

Low order byte

d15 d14 • • • • • d8

d7 • • • • • d0

MPS L14 • • • • • L8

L7 • • • • • L0

MPS :Prediction value MPS (0/1)

L14-0 :Low 15-bits of prediction unmatched probability LSZ

('0001' to '5b12')

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