U633H04SK45 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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U633H04SK45 Datasheet PDF : 13 Pages
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Preliminary
Read Cycle 1: Ai-controlled (during Read cycle: E = G = VIL, W = VIH)f
Ai
DQi
Output
Previus
Data Valid
1
tcR
Address Valid
2
ta(A)
9
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tv(A)
Read Cycle 2: G-, E-controlled (during Read cycle: W = VIH)g
Output Data
Valid
Ai
E
G
DQi
Output
ICC
High Impedance
ACTIVE
STANDBY
1
tcR
Address Valid
2
ta(A)
7
ten(E)
8
ten(G)
10
tPU
11
3
tPD
ta(E)
5
tdis(E)
4
ta(G)
6
tdis(G)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Output Data
Valid
U633H04
No.
Switching Characteristics
Write Cycle
12 Write Cycle Time
13 Write Pulse Width
14 Write Pulse Width Setup Time
15 Address Setup Time
16 Address Valid to End of Write
17 Chip Enable Setup Time
18 Chip Enable to End of Write
19 Data Setup Time to End of Write
20 Data Hold Time after End of Write
21 Address Hold after End of Write
22 W LOW to Output in High-Zh, i
23 W HIGH to Output in Low-Z
Symbol
Alt. #1 Alt. #2 IEC
tAVAV
tWLWH
tAVWL
tAVWH
tELWH
tDVWH
tWHDX
tWHAX
tWLQZ
tWHQX
tAVAV
tWLEH
tAVEL
tAVEH
tELEH
tDVEH
tEHDX
tEHAX
tcW
tw(W)
tsu(W)
tsu(A)
tsu(A-WH)
tsu(E)
tw(E)
tsu(D)
th(D)
th(A)
tdis(W)
ten(W)
25
45
Unit
Min. Max. Min. Max.
25
45
ns
20
35
ns
20
35
ns
0
0
ns
20
35
ns
20
35
ns
20
35
ns
12
20
ns
0
0
ns
0
0
ns
10
15 ns
5
5
ns
December 12, 1997
5
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