U633H04SK45 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG

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U633H04SK45

PowerStore 512 x 8 nvSRAM

Zentrum Mikroelektronik Dresden AG 

U633H04

Preliminary

Device Operation

The U633H04 has two separate modes of operation:

SRAM mode and nonvolatile mode. In SRAM mode,

the memory operates as a standard fast static RAM. In

nonvolatile mode, data is transferred from SRAM to

EEPROM (the STORE operation) or from EEPROM to

SRAM (the RECALL operation). In this mode SRAM

functions are disabled.

STORE cycles may be initiated under user control via a

HSB assertion and are also automatically initiated

when the power supply voltage level of the chip falls

below VSWITCH. RECALL operations are automatically

initiated upon power up and may occur also when VCCX

rises above VSWITCH after a low power condition.

SRAM READ

The U633H04 performs a READ cycle whenever E and

G are LOW and HSB and W are HIGH. The address

specified on pins A0 - A8 determines which of the 512

data bytes will be accessed. When the READ is initia-

ted by an address transition, the outputs will be valid

after a delay of tcR. If the READ is initiated by E or G,

the outputs will be valid at ta(E) or at ta(G), whichever is

later. The data outputs will repeatedly respond to

address changes within the tcR access time without the

need for transition on any control input pins, and will

remain valid until another address change or until E or

G is brought HIGH or W or HSB is brought LOW.

SRAM WRITE

A WRITE cycle is performed whenever E and W are

LOW and HSB is HIGH. The address inputs must be

stable prior to entering the WRITE cycle and must

remain stable until either E or W goes HIGH at the end

of the cycle. The data on pins DQ0 - 7 will be written

into the memory if it is valid tsu(D) before the end of a W

controlled WRITE or tsu(D) before the end of an E con-

trolled WRITE.

It is recommended that G is kept HIGH during the en-

tire WRITE cycle to avoid data bus contention on the

common I/O lines. If G is left LOW, internal circuitry will

turn off the output buffers tdis(W) after W goes LOW.

AUTOMATIC STORE

During normal operation, the U633H04 will draw cur-

rent from VCCX to charge up a capacitor connected to

the VCAP pin. This stored charge will be used by the

chip to perform a single STORE operation. If the

voltage on the VCCX pin drops below VSWITCH, the part

will automatically disconnect the VCAP pin from VCCX

and initiate a STORE operation.

Figure 1 shows the proper connection of capacitors for

automatic STORE operation. The charge storage capa-

citor should have a capacity of at least 100 µF (± 20 %)

at 6 V.

Each U633H04 must have its own 100 µF capacitor.

Each U633H04 must have a high quality, high fre-

quency bypass capacitor of 0.1 µF connected between

VCAP and VSS, using leads and traces that are as short

as possible. This capacitor do not replace the normal

expected high frequency bypass capacitor between the

power supply voltage and VSS.

In order to prevent unneeded STORE operations, auto-

matic STOREs as well as those initiated by externally

driving HSB LOW will be ignored unless at least one

WRITE operation has taken place since the most

recent STORE cycle. Note that if HSB is driven LOW

via external circuitry and no WRITEs have taken place,

the part will still be disabled until HSB is allowed to

return HIGH.

AUTOMATIC RECALL

During power up an automatic RECALL takes place. At

a low power condition (power supply voltage < VSWITCH)

an internal RECALL request may be latched. As soon

as power supply voltage exceeds again the sense

voltage of VSWITCH, a requested RECALL cycle will

automatically be initiated and will take tRESTORE to com-

plete.

If the U633H04 is in a WRITE state at the end of a

power up RECALL, the SRAM data will be corrupted.

To help avoid this situation, a 10 KΩ resistor should be

connected between W and power supply voltage.

10

December 12, 1997

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