VG3617161ET Просмотр технического описания (PDF) - Vanguard International Semiconductor

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VG3617161ET

1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM

Vanguard International Semiconductor  

VIS

VG3617161ET

1,048,576 x 16 - Bit

CMOS Synchronous Dynamic RAM

IDD Specifications (VDD = 3.3V ± 0.3V, TA = 0 ~ 70°C)

Description/test condition

Operating Current

tRC ≥ tRC(min), outputs open

Address changed once during tCK(min).

Burst length = 1 (One bank active)

Precharge Standby Current in non power-down

mode

CKE ≥ VIH (min), CS ≥ VIH (min), tCK =tCK(min)

Input signals are changed once during 2 clocks

Precharge Standby Current in non power-down

mode

CKE ≥ VIH (min), tCK = ∞ , CLK ≤ VIL (max)

Input signals are stable

Precharge Standby Current in power-down mode

CKE ≤ VIL (max), tCK = tCK(min)

Symbol

IDD1

IDD2N

IDD2NS

IDD2P

-6

Min Max

115

40

35

2

Precharge Standby Current in power-down mode IDD2PS

2

CKE ≤ VIL (max), tCK = ∞ , CLK ≤ VIL (max)

Active Standby Current in non power-down mode IDD3N

50

CKE ≥ VIH (min), CS ≥ VIH(min), tCK = tCK(min)

Input signals are changed once during 2 clocks

Active Standby Current in non power-down mode IDD3NS

40

CKE ≥ VIH (min), tCK = ∞ , CLK ≤ VIL (max)

Input signals are stable

Active Standby Current in power-down mode

IDD3P

35

≤ CKE VIL (max), tCK = tCK(min)

Active Standby Current in power-down mode

IDD3PS

35

CKE ≤ VIL (max), tCK = ∞ , CLK ≤ VIL (max)

Operating Current

(Page burst, and all banks activated)

tCCD = tCCD(min), outputs open, gapless data

Refresh Current

tRC ≥ tRC (min) (tREF = 64ms)

Self Refresh Current

CKE ≤ 0.2V

IDD4

150

IDD5

100

IDD6

1

-7

Min Max

105

40

35

2

2

50

40

35

35

140

90

1

-8

Min Max

95

Unit Note

3,4

40

3

35

mA

2

2

50

3

40

35

35

130

4,5

80

3

1

Document:1G5-0189

Rev.1

Page 5

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