M38504M6-SP Просмотр технического описания (PDF) - Renesas Electronics

Номер в каталоге

Компоненты Описание

Список матч

M38504M6-SP

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

APPENDIX

3.7 Machine instructions

Symbol

Function

BPL

N = 0?

(Note 4)

BRA

PC ← PC ± offset

BRK

BVC

(Note 4)

B←1

(PC) ← (PC) + 2

M(S) ← PCH

S←S–1

M(S) ← PCL

S←S–1

M(S) ← PS

S←S–1

I← 1

PCL ← ADL

PCH ← ADH

V = 0?

BVS

V = 1?

(Note 4)

CLB

Ai or Mi ← 0

CLC

C←0

CLD

D←0

CLI

I←0

CLT

T←0

CLV

V←0

CMP

(Note 3)

When T = 0

A–M

When T = 1

M(X) – M

COM

CPX

M

←

__

M

X–M

CPY

Y–M

DEC

A ← A – 1 or

M←M–1

Addressing mode

Details

IMP

IMM

A

BIT, A

ZP

BIT, ZP

OP n # OP n # OP n # OP n # OP n # OP n #

This instruction takes a branch to the ap-

pointed address if N is 0. The branch address

is specified by a relative address. If N is 1, the

next instruction is executed.

This instruction branches to the appointed ad-

dress. The branch address is specified by a

relative address.

When the BRK instruction is executed, the 00 7 1

CPU pushes the current PC contents onto the

stack. The BADRS designated in the interrupt

vector table is stored into the PC.

This instruction takes a branch to the ap-

pointed address if V is 0. The branch address

is specified by a relative address. If V is 1, the

next instruction is executed.

This instruction takes a branch to the ap-

pointed address when V is 1. The branch

address is specified by a relative address.

When V is 0, the next instruction is executed.

This instruction clears the designated bit i of A

or M.

This instruction clears C.

18 2 1

1+B 2 1

20i

1+F 5 2

20i

This instruction clears D.

D8 2 1

This instruction clears I.

58 2 1

This instruction clears T.

12 2 1

This instruction clears V.

B8 2 1

When T = 0, this instruction subtracts the con-

tents of M from the contents of A. The result is

not stored and the contents of A or M are not

modified.

When T = 1, the CMP subtracts the contents

of M from the contents of M(X). The result is

not stored and the contents of X, M, and A are

not modified.

M(X) represents the contents of memory

where is indicated by X.

This instruction takes the one’s complement of

the contents of M and stores the result in M.

This instruction subtracts the contents of M

from the contents of X. The result is not stored

and the contents of X and M are not modified.

This instruction subtracts the contents of M

from the contents of Y. The result is not stored

and the contents of Y and M are not modified.

This instruction subtracts 1 from the contents

of A or M.

C9 2 2

C5 3 2

E0 2 2

C0 2 2

1A 2 1

44 5 2

E4 3 2

C4 3 2

C6 5 2

3-70

3850 Group (Spec. H) User’s Manual

APPENDIX

3.7 Machine instructions

Addressing mode

Processor status register

ZP, X

ZP, Y

ABS ABS, X ABS, Y

IND ZP, IND IND, X IND, Y

REL

SP 7 6 5 4 3 2 1 0

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # N V T B D I Z C

10 2 2

••••••••

80 4 2

••••••••

• • •1•1• •

D5 4 2

CD 4 3 DD 5 3 D9 5 3

50 2 2

70 2 2

C1 6 2 D1 6 2

••••••••

••••••••

••••••••

• • • • • • •0

• • • •0• • •

• • • • •0• •

• •0• • • • •

•0• • • • • •

N • • • • • ZC

D6 6 2

EC 4 3

CC 4 3

CE 6 3 DE 7 3

3850 Group (Spec. H) User’s Manual

N• • • • •Z•

N • • • • • ZC

N • • • • • ZC

N• • • • •Z•

3-71

Share Link: