M38504M6-SP Просмотр технического описания (PDF) - Renesas Electronics

Номер в каталоге

Компоненты Описание

Список матч

M38504M6-SP

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

APPENDIX

3.5 List of registers

CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

1

CPU mode register

(CPUM: address 3B16)

b

Name

0 Processor mode

bits

1

2 Stack page

selection bit

3 Fix this bit to “1”.

Functions

b1 b0

00 : Single-chip mode

01 :

10 : Not available

11 :

0 : 0 page

1 : 1 page

4 Port Xc switch bit

0: I/O port function

(stop oscillating)

1: XCIN-XCOUT oscillation

function

5 Main clock (XIN-

XOUT) stop bit

6 Main clock division

ratio selection bits

7

0: Oscillating

1: Stopped

b7 b6

0 0: φ=f(XIN)/2

(high-speed mode)

0 1: φ=f(XIN)/8

(middle-speed mode)

1 0: φ=f(XCIN)/2

(low-speed mode)

1 1: not available

At reset R W

0

0

0

1

0

0

1

0

Fig. 3.5.26 Structure of CPU mode register

Interrupt request register 1

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register 1

(IREQ1 : address 3C16)

b

Name

Functions

At reset R W

0 INT0 interrupt

0 : No interrupt request issued

0

✽

request bit

1 : Interrupt request issued

1 When writing to this bit, set “0” to this bit.

0

✽

2 INT1 interrupt

0 : No interrupt request issued

0

✽

request bit

1 : Interrupt request issued

3 INT2 interrupt

0 : No interrupt request issued

0

✽

request bit

1 : Interrupt request issued

4 INT3/Serial I/O2

0 : No interrupt request issued

0

✽

interrupt request bit 1 : Interrupt request issued

5 When writing to this bit, set “0” to this bit.

0

✽

6 Timer X interrupt 0 : No interrupt request issued 0

✽

request bit

1 : Interrupt request issued

7 Timer Y interrupt 0 : No interrupt request issued 0

✽

request bit

1 : Interrupt request issued

✽: “0” can be set by software, but “1” cannot be set.

Fig. 3.5.27 Structure of Interrupt request register 1

3850 Group (Spec. H) User’s Manual

3-63

Share Link: