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R5F61582

Renesas 32-Bit CISC Microcomputer / Hardware Manual

Renesas Electronics 

13.5 Multiprocessor Communication Function......................................................................... 449

13.5.1 Multiprocessor Serial Data Transmission ......................................................... 451

13.5.2 Multiprocessor Serial Data Reception .............................................................. 452

13.6 Operation in Clocked Synchronous Mode ........................................................................ 455

13.6.1 Clock................................................................................................................. 455

13.6.2 SCI Initialization (Clocked Synchronous Mode) .............................................. 456

13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ................................. 457

13.6.4 Serial Data Reception (Clocked Synchronous Mode)....................................... 459

13.6.5 Simultaneous Serial Data Transmission and Reception

(Clocked Synchronous Mode) .......................................................................... 461

13.7 Operation in Smart Card Interface Mode.......................................................................... 463

13.7.1 Sample Connection ........................................................................................... 463

13.7.2 Data Format (Except in Block Transfer Mode) ................................................ 464

13.7.3 Block Transfer Mode ........................................................................................ 465

13.7.4 Receive Data Sampling Timing and Reception Margin.................................... 466

13.7.5 Initialization ...................................................................................................... 467

13.7.6 Data Transmission (Except in Block Transfer Mode) ...................................... 468

13.7.7 Serial Data Reception (Except in Block Transfer Mode).................................. 471

13.7.8 Clock Output Control........................................................................................ 472

13.8 Interrupt Sources............................................................................................................... 474

13.8.1 Interrupts in Normal Serial Communication Interface Mode ........................... 474

13.8.2 Interrupts in Smart Card Interface Mode .......................................................... 475

13.9 Usage Notes ...................................................................................................................... 476

13.9.1 Module Stop Mode Setting ............................................................................... 476

13.9.2 Break Detection and Processing ....................................................................... 476

13.9.3 Mark State and Break Detection ....................................................................... 476

13.9.4 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ................................................................. 476

13.9.5 Relation between Writing to TDR and TDRE Flag .......................................... 477

13.9.6 Restrictions on Using DTC or DMAC.............................................................. 477

13.9.7 SCI Operations during Mode Transitions ......................................................... 478

Section 14 Synchronous Serial Communication Unit (SSU) ............................481

14.1 Features............................................................................................................................. 481

14.2 Input/Output Pins.............................................................................................................. 483

14.3 Register Descriptions........................................................................................................ 484

14.3.1 SS Control Register H (SSCRH) ...................................................................... 486

14.3.2 SS Control Register L (SSCRL) ....................................................................... 488

14.3.3 SS Mode Register (SSMR) ............................................................................... 489

14.3.4 SS Enable Register (SSER) .............................................................................. 490

14.3.5 SS Status Register (SSSR) ................................................................................ 491

14.3.6 SS Control Register 2 (SSCR2) ........................................................................ 495

14.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)............................... 496

Rev. 2.00 Mar. 15, 2006 page xvii of xxxviii

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