R5F61582 Просмотр технического описания (PDF) - Renesas Electronics

Номер в каталоге

Компоненты Описание

Список матч

R5F61582

Renesas 32-Bit CISC Microcomputer / Hardware Manual

Renesas Electronics 

6.6 Write Data Buffer Function ............................................................................................... 130

6.6.1 Write Data Buffer Function for Peripheral Module.............................................. 130

6.7 Bus Arbitration .................................................................................................................. 131

6.7.1 Operation .............................................................................................................. 131

6.7.2 Bus Transfer Timing............................................................................................. 131

6.8 Bus Controller Operation in Reset ..................................................................................... 133

6.9 Usage Notes ....................................................................................................................... 133

Section 7 DMA Controller (DMAC)................................................................. 135

7.1 Features.............................................................................................................................. 135

7.2 Register Descriptions......................................................................................................... 138

7.2.1 DMA Source Address Register (DSAR) .............................................................. 139

7.2.2 DMA Destination Address Register (DDAR) ...................................................... 140

7.2.3 DMA Offset Register (DOFR).............................................................................. 141

7.2.4 DMA Transfer Count Register (DTCR) ............................................................... 142

7.2.5 DMA Block Size Register (DBSR) ...................................................................... 143

7.2.6 DMA Mode Control Register (DMDR)................................................................ 144

7.2.7 DMA Address Control Register (DACR)............................................................. 153

7.2.8 DMA Module Request Select Register (DMRSR) ............................................... 160

7.3 Transfer Modes .................................................................................................................. 160

7.4 Operations.......................................................................................................................... 161

7.4.1 Address Modes ..................................................................................................... 161

7.4.2 Transfer Modes..................................................................................................... 165

7.4.3 Activation Sources................................................................................................ 169

7.4.4 Bus Access Modes................................................................................................ 171

7.4.5 Extended Repeat Area Function ........................................................................... 172

7.4.6 Address Update Function using Offset ................................................................. 175

7.4.7 Register during DMA Transfer............................................................................. 179

7.4.8 Priority of Channels.............................................................................................. 184

7.4.9 DMA Basic Bus Cycle.......................................................................................... 185

7.4.10 Bus Cycles in Dual Address Mode ................................................................... 186

7.4.11 Bus Cycles in Single Address Mode................................................................. 194

7.5 DMA Transfer End ............................................................................................................ 199

7.6 Relationship among DMAC and Other Bus Masters ......................................................... 201

7.6.1 CPU Priority Control Function Over DMAC ....................................................... 201

7.6.2 Bus Arbitration among DMAC and Other Bus Masters ....................................... 202

7.7 Interrupt Sources................................................................................................................ 203

7.8 Notes on Usage .................................................................................................................. 206

Section 8 Data Transfer Controller (DTC)........................................................ 207

8.1 Features.............................................................................................................................. 207

8.2 Register Descriptions......................................................................................................... 209

8.2.1 DTC Mode Register A (MRA) ............................................................................. 210

Rev. 2.00 Mar. 15, 2006 page xii of xxxviii

Share Link: