R5F61582 Просмотр технического описания (PDF) - Renesas Electronics
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R5F61582 Datasheet PDF : 796 Pages
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8.2.2 DTC Mode Register B (MRB).............................................................................. 211
8.2.3 DTC Source Address Register (SAR)................................................................... 212
8.2.4 DTC Destination Address Register (DAR)........................................................... 213
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 213
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 214
8.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) ...................................... 214
8.2.8 DTC Control Register (DTCCR) .......................................................................... 216
8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 217
8.3 Activation Sources ............................................................................................................. 217
8.4 Location of Transfer Information and DTC Vector Table ................................................. 218
8.5 Operation ........................................................................................................................... 223
8.5.1 Bus Cycle Division ............................................................................................... 225
8.5.2 Transfer Information Read Skip Function ............................................................ 227
8.5.3 Transfer Information Writeback Skip Function .................................................... 228
8.5.4 Normal Transfer Mode ......................................................................................... 228
8.5.5 Repeat Transfer Mode........................................................................................... 229
8.5.6 Block Transfer Mode ............................................................................................ 231
8.5.7 Chain Transfer ...................................................................................................... 232
8.5.8 Operation Timing.................................................................................................. 233
8.5.9 Number of DTC Execution Cycles ....................................................................... 235
8.5.10 DTC Bus Release Timing ................................................................................. 236
8.5.11 DTC Priority Level Control to the CPU ........................................................... 236
8.6 DTC Usage Procedure ....................................................................................................... 237
8.6.1 Activation by Interrupt.......................................................................................... 237
8.7 Examples of Use of the DTC ............................................................................................. 238
8.7.1 Normal Transfer Mode ......................................................................................... 238
8.7.2 Chain Transfer ...................................................................................................... 239
8.7.3 Chain Transfer when Counter = 0......................................................................... 240
8.8 Interrupt Sources................................................................................................................ 241
8.9 Usage Notes ....................................................................................................................... 241
8.9.1 Module Stop Mode Setting ................................................................................... 241
8.9.2 On-Chip RAM ...................................................................................................... 241
8.9.3 DMAC Transfer End Interrupt.............................................................................. 242
8.9.4 DTCE Bit Setting.................................................................................................. 242
8.9.5 Chain Transfer ...................................................................................................... 242
8.9.6 Transfer Information Start Address, Source Address,
and Destination Address ....................................................................................... 242
8.9.7 Endian ................................................................................................................... 242
Section 9 I/O Ports .............................................................................................243
9.1 Register Descriptions ......................................................................................................... 249
9.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D, H, I, J, and K)............ 251
9.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D, H, I, J, and K)............................... 251
Rev. 2.00 Mar. 15, 2006 page xiii of xxxviii
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