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R5F61582

Renesas 32-Bit CISC Microcomputer / Hardware Manual

Renesas Electronics 

4.7.2 Exception Handling by General Illegal Instruction................................................. 79

4.8 Stack Status after Exception Handling................................................................................. 80

4.9 Usage Note........................................................................................................................... 80

Section 5 Interrupt Controller ..............................................................................83

5.1 Features................................................................................................................................ 83

5.2 Input/Output Pins ................................................................................................................. 85

5.3 Register Descriptions ........................................................................................................... 85

5.3.1 Interrupt Control Register (INTCR) ....................................................................... 86

5.3.2 CPU Priority Control Register (CPUPCR) ............................................................. 87

5.3.3 Interrupt Priority Registers A to G, I, K to O, Q, and R

(IPRA to IPRG, IPRI, IPRK to IPRO, IPRQ, and IPRR) ....................................... 89

5.3.4 IRQ Enable Register (IER) ..................................................................................... 91

5.3.5 IRQ Sense Control Registers H and L (ISCRH and ISCRL) .................................. 93

5.3.6 IRQ Status Register (ISR)....................................................................................... 98

5.3.7 Software Standby Release IRQ Enable Register (SSIER) ...................................... 99

5.4 Interrupt Sources................................................................................................................ 100

5.4.1 External Interrupts ................................................................................................ 100

5.4.2 Internal Interrupts ................................................................................................. 101

5.5 Interrupt Exception Handling Vector Table....................................................................... 102

5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 109

5.6.1 Interrupt Control Mode 0 ...................................................................................... 109

5.6.2 Interrupt Control Mode 2 ...................................................................................... 111

5.6.3 Interrupt Exception Handling Sequence ............................................................... 113

5.6.4 Interrupt Response Times ..................................................................................... 114

5.6.5 DTC and DMAC Activation by Interrupt ............................................................. 115

5.7 CPU Priority Control Function Over DTC and DMAC..................................................... 118

5.8 Usage Notes ....................................................................................................................... 121

5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 121

5.8.2 Instructions that Disable Interrupts ....................................................................... 122

5.8.3 Times when Interrupts are Disabled ..................................................................... 122

5.8.4 Interrupts during Execution of EEPMOV Instruction........................................... 122

5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123

5.8.6 Interrupt Flags of Peripheral Modules .................................................................. 123

Section 6 Bus Controller (BSC).........................................................................125

6.1 Features.............................................................................................................................. 125

6.2 Register Descriptions ......................................................................................................... 126

6.2.1 Bus Control Register 2 (BCR2) ............................................................................ 126

6.3 Bus Configuration.............................................................................................................. 127

6.4 Multi-Clock Function......................................................................................................... 128

6.5 Internal Bus........................................................................................................................ 129

6.5.1 Access to Internal Address Space ......................................................................... 129

Rev. 2.00 Mar. 15, 2006 page xi of xxxviii

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