CY7C1018DV33 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1018DV33

1-Mbit (128 K × 8) Static RAM

Cypress Semiconductor 

CY7C1018DV33

CY7C1019DV33

Switching Waveforms (continued)

Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18]

tWC

ADDRESS

CE

WE

DATA I/O

tSCE

tSA

tSCE

tAW

tHA

tPWE

tSD

tHD

DATA IN VALID

ADDRESS

CE

WE

Figure 8. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]

tWC

tSCE

tAW

tHA

tSA

tPWE

OE

DATA I/O NOTE 19

tHZOE

tSD

tHD

DATA IN VALID

Notes

17. Data I/O is high impedance if OE = VIH.

18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

19. During this period the I/Os are in the output state and input signals should not be applied.

Document Number: 38-05481 Rev. *J

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