CY7C1018DV33 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1018DV33

1-Mbit (128 K × 8) Static RAM

Cypress Semiconductor 

CY7C1018DV33

CY7C1019DV33

Switching Waveforms (continued)

Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [20, 21]

ADDRESS

CE

tWC

tSCE

tAW

tHA

tSA

tPWE

WE

DATA I/O

NOTE 22

tHZWE

tSD

DATA IN VALID

tHD

tLZWE

Notes

20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

21. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

22. During this period the I/Os are in the output state and input signals should not be applied.

Document Number: 38-05481 Rev. *J

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