CY7C1018DV33 Просмотр технического описания (PDF) - Cypress Semiconductor

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CY7C1018DV33

1-Mbit (128 K × 8) Static RAM

Cypress Semiconductor 

CY7C1018DV33

CY7C1019DV33

Switching Waveforms

Figure 5. Read Cycle No. 1 (Address Transition Controlled) [14, 15]

tRRCC

ADDRESS

DATA I/O

tAA

tOHA

PREVIOUS DATA VALID

DATA OUT VALID

ADDRESS

CE

OE

DATA I/O

VCC

SUPPLY

CURRENT

Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16]

tRC

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

tHZOE

tHZCE

DATA OUT VALID

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes

14. Device is continuously selected. OE, CE = VIL.

15. WE is HIGH for Read cycle.

16. Address valid prior to or coincident with CE transition LOW.

Document Number: 38-05481 Rev. *J

Page 8 of 20

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