CY62146EV30LL(2009) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY62146EV30LL
(Rev.:2009)

4-Mbit (256K x 16) Static RAM

Cypress Semiconductor 

CY62146EV30 MoBL®

Switching Waveforms

Figure 5. Read Cycle 1 (Address Transition Controlled) [15, 16]

tRC

ADDRESS

DATA OUT

tOHA

tAA

PREVIOUS DATA VALID

DATA VALID

Figure 6. Read Cycle No. 2 (OE Controlled) [16, 17]

ADDRESS

CE

OE

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGHIMPEDANCE

tLZCE

tPU

50%

DATA VALID

tPD

tHZCE

tHZOE

tHZBE

HIGH

IMPEDANCE

ICC

50%

ISB

Notes

15. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL.

16. WE is HIGH for read cycle.

17. Address valid before or similar to CE and BHE, BLE transition LOW.

Document Number: 38-05567 Rev. *D

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