CY62146EV30LL(2009) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY62146EV30LL Datasheet PDF : 13 Pages
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Switching Characteristics
Over the Operating Range [10, 11]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle [14]
tWC
tSCE
tAW
tHA
tSA
tPWE
tBW
tSD
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z [12]
OE HIGH to High-Z [12, 13]
CE LOW to Low-Z [12]
CE HIGH to High-Z [12, 13]
CE LOW to Power Up
CE HIGH to Power Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low-Z [12]
BLE / BHE HIGH to High-Z [12, 13]
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
BLE / BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z [12, 13]
WE HIGH to Low-Z [12]
CY62146EV30 MoBL®
45 ns (Industrial/Auto-A)
Min
Max
Unit
45
ns
45
ns
10
ns
45
ns
22
ns
5
ns
18
ns
10
ns
18
ns
0
ns
45
ns
22
ns
5
ns
18
ns
45
ns
35
ns
35
ns
0
ns
0
ns
35
ns
35
ns
25
ns
0
ns
18
ns
10
ns
Notes
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
11. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
13. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state.
14. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 38-05567 Rev. *D
Page 5 of 13
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