PTN3460 Просмотр технического описания (PDF) - NXP Semiconductors.

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PTN3460

eDP to LVDS bridge IC

NXP Semiconductors. 

NXP Semiconductors

PTN3460

eDP to LVDS bridge IC

Table 2. Pin description …continued

Symbol

Pin Type

Description

MS_SDA 24

open-drain (I2C) I2C-bus data signal connection to I2C-bus master or slave. Pulled up by external

data input/output resistor.

MS_SCL 25

open-drain (I2C) I2C-bus clock signal connection to I2C-bus master or slave. Pulled up by

clock input/output external resistor.

n.c.

55

-

not connected; reserved.

EPS_N

56

input

Can be left open or pulled HIGH for 3.3 V supply only option relying on internal

regulator for 1.8 V generation.

Should be pulled down to GND for dual supply (3.3 V/1.8 V) option.

Supply, ground and decoupling

VDD(3V3)

13, 14, power

38, 50

3.3 V supply input.

VDD(1V8)

VDD(1V8)

n.c.

6, 45

19

15, 16

power

power

power

1.8 V supply input.

1.8 V regulator supply output.

Not connected.

GND

3

power

Ground.

GNDREG 17, 18 power

Ground for regulator.

GND

center power

pad

The center pad must be connected to motherboard GND plane for both

electrical ground and thermal relief.

8. Functional description

PTN3460 is an (Embedded) DisplayPort to LVDS bridge IC that processes the incoming

DisplayPort (DP) stream, performs DP to LVDS protocol conversion and transmits

processed stream in LVDS format. Refer to Figure 2 “Block diagram of PTN3460”.

The PTN3460 consists of:

• DisplayPort receiver

• LVDS transmitter

• System control and operation

The following sections describe individual sub-systems and their capabilities in more

detail.

8.1 DisplayPort receiver

PTN3460 implements a DisplayPort receiver consisting of 2-lane Main Link and AUX

channel.

With its advanced signal processing capability, it can handle Fast Link training or Full Link

training scheme. PTN3460 implements a high-performance Auto Receive Equalizer and

Clock Data Recovery (CDR) algorithm, with which it identifies and selects an optimal

operational setting for given channel environment. Given that the device is targeted

primarily for embedded Display connectivity, both Display Authentication and Copy

Protection Method 3a (Alternate Scrambler Seed Reset) and Method 3b (Enhanced

Framing) are supported, as per eDP 1.2.

PTN3460

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 12 March 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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