W83194BR-703 Просмотр технического описания (PDF) - Winbond
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W83194BR-703 Datasheet PDF : 28 Pages
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W83194BR-703/W83194BG-703
Table-2 CPU, ZCLK divider ratio selection Table
LSB
ZCLK
BIT5
MSB
0
1
Bit2/
0
Bit4/
1
Bit9
Div3
Div5
Div4
Div6
00
Div2
Div6
CPU
BIT1, 0
01
10
Div3
Div4
Div8
Div8
11
Div5
Div8
7.14 Register 13: M/N Control (Default: 0Ah)
BIT
NAME
PWD
DESCRIPTION
0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
7 EN_MN_PROG 0 VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be clear. Then
the frequency will be decided by hardware default FS<4:0>
or desired frequency select SAF_FREQ [4:0] depend on
EN_SAFE_FREQ (Reg0 - bit 7).
6 NVAL<10>
X Programmable N divisor bit 10.
5 DIVM_P1
4 DIVM_P0
0 Variable accumulation period for M divisor. Depend
On VCO Frequency.
0 00: 400M
01: 533M
10: 667M
11: 800M
3 IVAL<3>
X
2 IVAL<2>
1 IVAL<1>
X Charge pump current selection
X
0 IVAL<0>
X
- 13 -
Publication Release Date: Jan. 2006
Revision 0.8
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