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VT82C586B

PCI Integrated Peripheral Controller

Unspecified 

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VT82C586B

UltraDMA-33 Enhanced IDE Interface

Signal Name

Pin No.

I/O Signal Description

DRDYA# /

49

DDMARDYA#

I EIDE Mode:

I/O Channel Ready A. Primary channel device ready indicator

UltraDMA Mode: Device DMA Ready A. Primary channel output flow control

/ DSTROBEA

The device may assert DDMARDY# to pause output transfers

Device Strobe A. Primary channel input data strobe (both edges)

The device may stop DSTROBE to pause input data transfers

DRDYB# /

89

DDMARDYB#

/ DSTROBEB

I EIDE Mode:

I/O Channel Ready B. Secondary channel device ready

UltraDMA Mode: Device DMA Ready B. Secondary channel output flow control

The device may assert DDMARDY# to pause output transfers

Device Strobe B. Secondary channel input strobe (both edges)

The device may stop DSTROBE to pause input data transfers

DIORA# /

50

O EIDE Mode:

Device I/O Read A. Primary channel device read strobe

HDMARDYA#

UltraDMA Mode: Host DMA Ready A. Primary channel input flow control

/ HSTROBEA

The host may assert HDMARDY# to pause input transfers

Host Strobe A. Primary channel output data strobe (both edges)

The host may stop HSTROBE to pause output data transfers

DIORB# /

54

O EIDE Mode:

Device I/O Read B. Secondary channel device read strobe

HDMARDYB#

UltraDMA Mode: Host DMA Ready B. Secondary channel input flow control

/ HSTROBEB

The host may assert HDMARDY# to pause input transfers

Host Strobe B. Secondary channel output strobe (both edges)

The host may stop HSTROBE to pause output data transfers

DIOWA# /

51

O EIDE Mode:

Device I/O Write A. Primary channel device write strobe

STOPA

UltraDMA Mode: Stop A. Primary channel stop transfer: asserted by the host prior

to initiation of an UltraDMA burst; negated by the host before

data is transferred in an UltraDMA burst. Assertion of STOP by

the host during or after data transfer in UltraDMA mode signals

the termination of the burst.

DIOWB# /

STOPB

55

O EIDE Mode:

Device I/O Write B. Secondary channel device write strobe

UltraDMA Mode: Stop B. Secondary channel stop transfer: asserted by the host

prior to initiation of an UltraDMA burst; negated by the host

before data is transferred in an UltraDMA burst. Assertion of

STOP by the host during or after data transfer in UltraDMA mode

signals the termination of the burst.

SOE#

56

O System Address Transceiver Output Enable. This signal controls the output

enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The

transceiver direction controls are driven by MASTER# with DD[15-0] connected to

the “A” side of the transceivers and SA[15-0] connected to the “B” side.

DDRQA

45

I Device DMA Request A. Primary channel DMA request

DDRQB

46

I Device DMA Request B. Secondary channel DMA request

DDACKA#

47

O Device DMA Acknowledge A. Primary channel DMA acknowledge

DDACKB#

48

O Device DMA Acknowledge B. Secondary channel DMA acknowledge

Note: Refer to the ISA bus interface pin descriptions for remaining IDE interface pin descriptions (the IDE address, data, and

drive select pins are multiplexed with the ISA bus LA and SA pins). Also, the MASTER# pin description may be found

in the "On Board Plug and Play" pin group (DD / SA transceiver direction control).

Revision 1.0 May 13, 1997

-10-

Pinouts

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