UPD72870AF1 Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD72870AF1

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870A

1.9 VDD

Name

PCI_VDD

L_VDD

P_DVDD

P_AVDD

I/O

Pin No.

LQFP

FBGA

- 10,31,51,70

E3,F3,N3,N6,

N11,N12,P6

- 1,20,40,46,59,72,81, A2,C5,J4,K4,L4,N5,

151

N9,N10,N13,P3,R16

- 97,103,107,108,149 A5,G13,G14,G16,

H14,K13,K14,L13

- 111

F15

- 116

D14

- 120,125

C15,D11-D13

- 146-148

B6,C6,D6

IOL Volts(V)

Function

- 5/3.3 VDD for PCI I/Os

Link

-

3.3 VDD for Link digital Core and

Link

Link I/Os

-

3.3 PHY digital VDD

PHY Digital

-

3.3 PHY PLL VDD

-

3.3 PHY PLL, OSC VDD

-

3.3 PHY Bias VDD

-

3.3 PHY Port VDD

PHY Analog

PHY Analog

PHY Analog

PHY Analog

1.10 GND

Name

DGND

AGND

I/O

Pin No.

IOL Volts(V)

Function

LQFP

FBGA

- 9,15,21,28,34,41,48, B5,D3,D5,E4,F4,F13, -

- Digital GND

54,65,71,80,85,90,98, F14,G3,G4,H3,H4,

104,109,150,152,160 H15,J3,J13,K3,L3,

M3,M4,M15,N4,N7,

N8,N14,P4,P5,P7,P8,

P10-P12,T16

- 112

E13

-

- PHY PLL GND

- 113

E14

-

- PHY PLL, OSC GND

- 119,124

B15,C16

-

- PHY Bias GND

- 141

A7

-

- PHY Common GND

- 142

B7

-

- PHY Speed Signal GND

- 143,144,145

A6,C7-C13,D7-D10

-

- PHY Port GND

[Caution]

*1: If the Link pin is pulled up, it should be connected to L_VDD.

*2: If the PHY Digital pin is pulled up, it should be connected to P_DVDD.

*3: If the PHY Analog pin is pulled up, it should be connected to P_AVDD.

16

Preliminary Data Sheet S14653EJ1V0DS00

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