UPD72870AF1 Просмотр технического описания (PDF) - NEC => Renesas Technology

Номер в каталоге

Компоненты Описание

Список матч

UPD72870AF1

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870A

Name

DEVSEL

STOP

PME

CLKRUN

INTA

PERR

SERR

PRST

PCLK

I/O

Pin No.

LQFP

FBGA

I/O 39

T1

I/O 42

T2

O3

B2

I/O 2

A1

O4

B1

I/O 43

R3

O 44

T3

I5

C2

I6

C1

IOL

Volts(V)

Function

PCI/Cardbus

PCI/Cardbus

PCI/Cardbus

PCI/Cardbus

PCI/Cardbus

PCI/Cardbus

PCI/Cardbus

-

-

5/3.3

5/3.3

5/3.3

5/3.3

5/3.3

5/3.3

5/3.3

5/3.3

5/3.3

Device Select when actively driven, indicates that

the driving device has decoded its address as the

target of the current access.

PCI Stop when actively driven, indicates that the

target is requesting the current bus master to stop

the transaction.

PME Output for power management enable.

PCICLK Running as input, to determine the status

of PCLK; as output, to request starting or speeding

up clock.

Interrupt the PCI interrupt request A.

Parity Error is used for reporting data parity errors

during all PCI transactions, except a Special Cycle.

It is an output when AD0-AD31 and PAR are both

inputs. It is an input when AD0-AD31 and PAR are

both outputs.

System Error is used for reporting address parity

errors, data parity errors during the Special Cycle,

or any other system error where the effect can be

catastrophic. When reporting address parity errors,

it is an output.

Reset PCI reset

PCI Clock 33 MHz system bus clock.

(2/2)

Link

Link

Link

Link

Link

Link

Link

Link

Link

1.2 Cable Interface Signals: (15 pins)

Name

I/O

Pin No.

IOL

LQFP

FBGA

TpA0p

I/O 140

B8

-

TpA0n

I/O 139

A8

-

TpB0p

I/O 138

B9

-

TpB0n

I/O 137

A9

-

TpA1p

I/O 136

B10

-

TpA1n

I/O 135

A10

-

TpB1p

I/O 134

B11

-

TpB1n

I/O 133

A11

-

TpA2p

I/O 132

B12

-

TpA2n

I/O 131

A12

-

TpB2p

I/O 130

B13

-

TpB2n

I/O 129

A13

-

Volts(V)

Function

(1/2)

-

Port-1 Twisted Pair A Positive Input/Output Note

*2

PHY Analog

-

Port-1 Twisted Pair A Negative Input/Output Note PHY Analog

-

Port-1 Twisted Pair B Positive Input/Output Note PHY Analog

-

Port-1 Twisted Pair B Negative Input/Output Note PHY Analog

-

Port-2 Twisted Pair A Positive Input/Output Note PHY Analog

-

Port-2 Twisted Pair A Negative Input/Output Note PHY Analog

-

Port-2 Twisted Pair B Positive Input/Output Note PHY Analog

-

Port-2 Twisted Pair B Negative Input/Output Note PHY Analog

-

Port-3 Twisted Pair A Positive Input/Output Note PHY Analog

-

Port-3 Twisted Pair A Negative Input/Output Note PHY Analog

-

Port-3 Twisted Pair B Positive Input/Output Note PHY Analog

-

Port-3 Twisted Pair B Negative Input/Output Note PHY Analog

Note If unused port, please refer to 4.1.4 Unused Ports.

Preliminary Data Sheet S14653EJ1V0DS00

13

Share Link: