IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
5V
From Output
Under Test
680 Ω
1.1 k Ω
(1)
30 pF
PROPAGATION DELAY
LOAD CIRCUIT
Timing
Input
Data,
Enable
Input
tS
1.5 V
1.5 V
th
3V
GND
1.5 V
3V
GND
High-Level
Input
Low-Level
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
tW
1.5 V
1.5 V
3V
GND
1.5 V
3V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Enable
1.5 V
tPLZ
Low-Level
Output
High-Level
Output tPHZ
1.5 V
tPZL
tPZH
1.5 V
1.5 V
3V
GND
≈3 V
VOL
VOH
≈ OV
Input
In-Phase
Output
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1.5 V
tPD
1.5 V
1.5 V
tPD
3V
GND
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3145 drw 20
NOTE:
1. Includes probe and jig capacitance.
Figure 20. Load Circuit and Voltage Waveforms
28