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IDT723613L30PQF

CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Integrated Device Technology 

IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING

64 x 36

COMMERCIAL TEMPERATURE RANGES

CLKB

CSB

W/RB

SIZ1,

SIZ0

ENB

tCLK

tCLKH

tCLKL

LOW

LOW

LOW

tENS

tENH

EF HIGH

tA

B0 -B35 Previous Word in FIFO Output Register

tSKEW1(1)

CLKA

FF

FIFO Full

Next Word From FIFO

tCLK

tCLKH

tCLKL

1

2

tWFF

tWFF

CSA LOW

WRA HIGH

MBA

tENS

tENH

tENS

tENH

ENA

tDS

tDH

A0 - A35

To FIFO

3145 drw 10

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown.

2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising

CLKB edge that reads the last word or byte of the long word, respectively.

Figure 10. FF Flag Timing and First Available Write when the FIFO is Full

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