STK12C68 Просмотр технического описания (PDF) - Cypress Semiconductor
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STK12C68 Datasheet PDF : 24 Pages
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STK12C68
Device Operation
The STK12C68 nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK12C68 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6V should be
provided. The voltage on the VCAP pin is driven to 5V by a charge
pump internal to the chip. A pull up is placed on WE to hold it
inactive during power up.
Figure 2. AutoStore Mode
. SRAM Read
only The STK12C68 performs a Read cycle whenever CE and OE are
s LOW while WE and HSB are HIGH. The address specified on
am pins A0–12 determines the 8,192 data bytes accessed. When the
r Read is initiated by an address transition, the outputs are valid
rog after a delay of tAA (Read cycle 1). If the Read is initiated by CE
p or OE, the outputs are valid at tACE or at tDOE, whichever is later
n (Read cycle 2). The data outputs repeatedly respond to address
. tio changes within the tAA access time without the need for transi-
ns uc tions on any control input pins, and remains valid until another
ig od address change or until CE or OE is brought HIGH, or WE or
es pr HSB is brought LOW.
w D ing SRAM Write
Ne ngo A Write cycle is performed whenever CE and WE are LOW and
for t o HSB is HIGH. The address inputs must be stable prior to entering
d or the Write cycle and must remain stable until either CE or WE
de pp goes HIGH at the end of the cycle. The data on the common I/O
en su pins DQ0–7 are written into the memory if it has valid tSD, before
m to the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
com tion avoid data bus contention on common I/O lines. If OE is left LOW,
e c internal circuitry turns off the output buffers tHZWE after WE goes
R u LOW.
NoItn prod AutoStore Operation
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In system power mode, both VCC and VCAP are connected to the
+5V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK12C68 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6V during the 10 ms
The STK12C68 stores data to nvSRAM using one of three STORE cycle.
storage operations:
1. Hardware store activated by HSB
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations are ignored, unless at least one Write
2. Software store activated by an address sequence
operation has taken place since the most recent STORE or
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the STK12C68.
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a Write operation has taken place. An
optional pull up resistor is shown connected to HSB. The HSB
signal is monitored by the system to detect if an AutoStore cycle
is in progress.
Document Number: 001-51027 Rev. *C
Page 4 of 24
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