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SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

Timing specification

The internal delays of the output signals referred to the respective clock are given in Table 8.

handbook, full pagewidth

CLK

OUT

tPLH

tPHL

tPD

Fig.11 Timing diagram.

MGH140

Table 8 Delay table.

Conditions: VDD = +4.5 V; Tj =+70 °C (worst case).

CLK

OUT

LOAD

(pF)

LLA

SWC1

15

LLD

SRC

45

LLDFL

SRC

45

SRC

SWC2

25

SWC1

WE1

15

SWC2

WE2

10

SRC

RE1

10

SRC

RE2

10

LLDFL

HDFL

25

LLDFL

HRDFL

10

SWC1

HRA

10

SRC

HRD

10

SRC

BLND

25

SWC1

ALDUV

25

LLDFL

VB

25

SWC1

CLV

25

LLDFL

VDFL

25

LLA

WE1(EXT)

25

tPLH

(ns)

6.4

11.2

11.9

3.2

15.9

8.0

7.0

7.2

12.8

11.9

6.5

5.6

7.4

11.5

28.2

8.3

24.6

18.1

tPHL

(ns)

−

−

−

−

18.9

10.9

8.6

8.7

15.8

13.9

8.4

7.6

10.3

14.0

30.3

11.3

27.6

21.1

tPD

(ns)

6.5

13.7

13.9

2.6

−

−

−

−

−

−

−

−

−

−

−

−

−

−

April 1994

19

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