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SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

RE1

The output RE1 is the read enable signal for field

memory 1. A HIGH level enables the picture data to be

read from the memory. RE1 is a composite signal and

includes the horizontal read enable timing as well as the

vertical timing. It is possible to delay the horizontal timing

of RE1 up to three steps of LLD clock pulses.

Furthermore the vertical timing can be set one or two lines

before RE2 respectively one line after RE2 (median

filtering, noise reduction mode).

RE2

The output RE2 is the read enable signal for field

memory 2. A HIGH level enables the picture data to be

read from memory 2. RE2 is a composite signal and

includes the horizontal read enable timing as well as the

vertical timing. The horizontal timing of RE2 can be

delayed up to three steps of LLD clock pulses.

handbook, full pagewidth

VACQ

VDSP

VDSPr

RSTW2

VDSPf

Fig.9 Vertical display timing (VDSP = VWE2, VRE1/2 or VDFL).

MGH138

Table 7 Vertical programming range for display signals (VDSP = WE2, RE1 or RE2; see also Fig.9).

50 Hz

60 Hz

VDSPr = Nr × Line

VDSPf = Nf × Line

VDSPr = Nr × Line

VDSPf = Nf × Line

1 ≤ Nr < 311

1 < Nf ≤ 311

1 ≤ Nr < 261

1 < Nf ≤ 261

Nr ≠ Nf

RSTW2

The reset write output pulse 2 starts the write address

pointer of field memory 2. There are two functions possible

for this pin. If a serial structure of the memories is

implemented, RSTW2 is a 100 Hz pulse; in progressive

scan mode and with one field memory, RSTW2 is a 50 Hz

pulse. The pulse duration of RSTW2 is 32 µs (PAL).

April 1994

17

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