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SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

handbook, full pageLwLiAdth

HRA

ALDUV

(format 4:1:1)

ALDUV

(format 4:2:2)

ALDUV

(format 4:4:4)

Fig.5 Timing of the signal ALDUV.

MGH134

In case of an external write enable signal WEXT this output

provides a vertical blanking signal, which can be used to

generate a sandcastle pulse. The settings for the blanking

signal are done with the registers VWE1STA (falling edge)

and VWE1STO (rising edge).

CLV

The horizontal video clamping output pulse is generated

by the acquisition clock signal LLA and is used as clamp

pulse for the incoming luminance and chrominance signals

Y, U, V of the three analog to digital converters. The time

reference of CLV is the LOW-to-HIGH transition of the

HRA signal.

HRA/BLNA

The horizontal reference output pulse HRA operates on

the two standards PAL and NTSC.

In the PAL standard HRA has a frequency of 15.625 kHz

and in the NTSC standard the frequency is 15.734 kHz. In

both cases the duty cycle of this signal is 50%.

When the memory controller circuit is operating in a digital

environment, a horizontal reference signal BLNA and a

suitable acquisition clock pulse have to be supplied from

the external used circuits (i. e. SAA7151A, DMSD and

SAA7157, CGC).

WE1

A HIGH level on this output pin enables picture data to be

written to field memory 1. WE1 is a composite signal,

which includes the horizontal write enable signal as well as

the vertical one.

It is possible to delay the horizontal timing of WE1 up to

three LLA clock cycles. In case of an external write enable

signal WEXT the horizontal and vertical settings and the

delay control have no influence on WE1.

WE1 operates at a vertical frequency of 50 Hz. When the

progressive scan mode is activated, WE1 is disabled

every second field. In still picture mode this signal is set to

LOW level.

IE1

This output signal is used as a data input enable for

memory 1. A logic HIGH level on this output pin enables

the data information to be written into field memory 1. Via

signal IE1 the still picture function is controlled. When this

mode is selected, IE1 is switched to LOW level. It is

possible to disable the still picture mode with externally

supplied STROBE pulses.

April 1994

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