SAA4951 Просмотр технического описания (PDF) - Philips Electronics
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SAA4951 Datasheet PDF : 25 Pages
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Philips Semiconductors
Memory controller
Preliminary specification
SAA4951
BLND
The output signal BLND is a horizontal blanking pulse and
is used for the peripheral circuits NORIC and BENDIC.
A LOW level indicates the blanking interval, a HIGH level
indicates valid data from the memories. It is possible to
delay the horizontal timing of BLND up to three steps of
LLD clock pulses.
WE2
A HIGH level on this output pin enables picture data to be
written to field memory 2. WE2 is a composite signal,
which includes the horizontal write enable signal as well as
the vertical one.
The horizontal timing of WE2 can be delayed up to three
steps of LLD clock pulses.
The WE2 output signal is used in different modes. When
two field memories are implemented in a serial structure,
WE2 operates at a vertical frequency of 100 Hz. In case
two field memories are connected in parallel, WE2 has a
vertical frequency of 50 Hz. In the progressive scan mode
the WE2 signal is disabled every second field.
handbook, full pagewidth
HRD
HDSP
HDSPr
HDSPf
Fig.8 Programmable horizontal display signals (HDSP = BLN, WE2, RE1 or RE2).
MGH137
Table 6 Horizontal programming range for display signals (HDSP = BLN, WE2, RE1 or RE2; see also Fig.8).
27 MHz, 50 Hz
27 MHz, 60 Hz
32 MHz
36 MHz, 50 Hz
36 MHz, 60 Hz
HDSPr = (2Nr + 2) × LLD
HDSPf = (2Nf + 2) × LLD
HDSPr = (2Nr + 2) × LLD
HDSPf = (2Nf + 2) × LLD
HDSPr = (2Nr + 2) × LLD
HDSPf = (2Nf + 2) × LLD
HDSPr = (4Nr + 4) × LLD
HDSPf = (4Nf + 4) × LLD
HDSPr = (4Nr + 4) × LLD
HDSPf = (4Nf + 4) × LLD
0 ≤ Nr < 431
0 < Nf ≤ 431
0 ≤ Nr < 428
0 < Nf ≤ 428
0 ≤ Nr < 511
0 < Nf ≤ 511
0 ≤ Nr < 287
0 < Nf ≤ 287
0 ≤ Nr < 285
0 < Nf ≤ 285
Nr ≠ Nf
IE2
This output signal is used as data input enable for
memory 2. A logic HIGH level on this output pin enables
the data information to be written to field memory 2.
April 1994
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