NB6L11S Просмотр технического описания (PDF) - ON Semiconductor
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NB6L11S Datasheet PDF : 10 Pages
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NB6L11S
Table 5. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V, GND = 0 V; (Note 10)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPPmin) fin ≤ 1.0 GHz 220 350
220 350
220 350
mV
(Figure 4)
fin= 1.5 GHz 200 300
200 300
200 300
fin= 2.0 GHz 170 270
170 270
170 270
fDATA Maximum Operating Data Rate
1.5 2.5
1.5 2.5
1.5 2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
250
450 250
450 250
450 ps
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device−to−Device Skew (Note 15)
8 45
5 25
30 100
8 45
5 25
30 100
8 45 ps
5 25
30 100
tJITTER
VINPP
RMS Random Clock Jitter (Note 13) fin = 1.0 GHz
fin = 1.5 GHz
Deterministic Jitter (Note 14) fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
Input Voltage Swing/Sensitivity
100
(Differential Configuration) (Note 12)
0.5
0.5
6
7
10
VCC− 100
GND
0.5
0.5
6
7
10
VCC− 100
GND
0.5
0.5
ps
6
7
10
VCC− mV
GND
tr
Output Rise/Fall Times @ 250 MHz
tf
(20% − 80%)
Q, Q 70 120 170 70 120 170 70 120 170 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPPmin with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
12. Input voltage swing is a single−ended measurement operating in differential mode.
13. RMS jitter with 50% Duty Cycle input clock signal.
14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15. Skew is measured between outputs under identical transition @ 250 MHz.
16. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
400
350
300
−40°C
250
200
85°C
25°C
150
100
50
0
0
0.5
1
1.5
2
2.5
3
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 2.5 V)
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