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NB6L11S

2.5 V 1:2 AnyLevel Input to LVDS Fanout Buffer / Translator

ON Semiconductor 

NB6L11S

Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS VCC = 2.375 V to 2.625 V, GND = 0 V,

TA = −40°C to +85°C

Symbol

Characteristic

Min

Typ

Max

Unit

ICC

Power Supply Current (Note 8)

DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18)

30

45

mA

Vth

Input Threshold Reference Voltage Range (Note 7)

VIH

Single−ended Input HIGH Voltage

VIL

Single−ended Input LOW Voltage

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)

GND +100

Vth + 100

GND

VCC − 100 mV

VCC

mV

Vth − 100 mV

VIHD

Differential Input HIGH Voltage

VILD

Differential Input LOW Voltage

VCMR Input Common Mode Range (Differential Configuration)

VID

Differential Input Voltage (VIHD − VILD)

RTIN

Internal Input Termination Resistor

LVDS OUTPUTS (Note 4)

100

VCC

mV

GND

VCC − 100 mV

GND + 50

VCC − 50 mV

100

VCC

mV

40

50

60

W

VOD

Differential Output Voltage

250

450

mV

DVOD Change in Magnitude of VOD for Complementary Output States (Note 9)

0

1

25

mV

VOS

Offset Voltage (Figure 15)

1125

1375

mV

DVOS Change in Magnitude of VOS for Complementary Output States (Note 9)

0

1

25

mV

VOH

Output HIGH Voltage (Note 5)

1425

1600

mV

VOL

Output LOW Voltage (Note 6)

900

1075

mV

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14.

5. VOHmax = VOSmax + ½ VODmax.

6. VOLmax = VOSmin − ½ VODmax.

7. Vth is applied to the complementary input when operating in single−ended mode.

8. Input termination pins open, D/D at the DC level within VCMR and output pins loaded with RL = 100 W across differential.

9. Parameter guaranteed by design verification not tested in production.

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