NB6L11S Просмотр технического описания (PDF) - ON Semiconductor
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NB6L11S Datasheet PDF : 10 Pages
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NB6L11S
VCC VCC VCC VCC
16 15 14 13
Exposed Pad (EP)
Q0 1
Q0 2
Q1 3
Q1 4
NB6L11S
12 VTD
11 D
10 D
9 VTD
5 678
VCC NC VEE VEE
Figure 3. NB6L11S Pinout, 16−pin QFN (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q0
LVDS Output
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
2
Q0
LVDS Output
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
3
Q1
LVDS Output
Non−inverted D output. Typically loaded with 100 W receiver termination
resistor across differential pair.
4
Q1
LVDS Output
Inverted D output. Typically loaded with 100 W receiver termination resistor
across differential pair.
5
VCC
6
NC
−
Positive Supply Voltage.
No Connect.
7
VEE
Negative Supply Voltage.
8
VEE
Negative Supply Voltage.
9
VTD
−
Internal 50 W termination pin for D.
10
D
LVPECL, CML, LVDS,
Inverted Differential Clock/Data Input (Note 1).
LVCMOS, LVTTL
11
D
LVPECL, CML, LVDS,
Non−inverted Differential Clock/Data Input (Note 1).
LVCMOS, LVTTL
12
VTD
−
Internal 50 W termination pin for D.
13
VCC
−
Positive Supply Voltage.
14
VCC
−
Positive Supply Voltage.
15
VCC
−
Positive Supply Voltage.
16
VCC
−
Positive Supply Voltage.
EP
Exposed pad. The exposed pad (EP) on the package bottom must be
attached to a heat−sinking conduit. The exposed pad may only be
electrically connected to VEE.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
http://onsemi.com
2
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