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MM74HC374 Просмотр технического описания (PDF) - Fairchild Semiconductor

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MM74HC374
Fairchild
Fairchild Semiconductor Fairchild
MM74HC374 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
AC Electrical Characteristics
VCC 2.06.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA 25qC
Typ
TA 40 to 85qC TA 55 to 125qC Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
CL 50 pF
2.0V
4.5V
6
5
30
24
4
MHz
20
MHz
6.0V
35
28
23
MHz
tPHL, tPLH Maximum Propagation
Delay, Clock to Q
tPZH, tPZL Maximum Output
Enable Time
tPHZ, tPLZ Maximum Output
Disable Time
CL 50 pF
CL 150 pF
CL 50 pF
CL 150 pF
CL 50 pF
CL 150 pF
RL 1 k:
CL 50 pF
CL 150 pF
CL 50 pF
CL 150 pF
CL 50 pF
CL 150 pF
RL 1 k:
CL 50 pF
2.0V
68
180
225
2.0V
110
230
288
4.5V
22
36
45
4.5V
30
46
57
6.0V
20
31
39
6.0V
28
40
50
2.0V
50
150
189
2.0V
80
200
250
4.5V
21
30
37
4.5V
30
40
50
6.0V
19
26
31
6.0V
26
35
44
2.0V
50
150
189
4.5V
21
30
37
6.0V
19
26
31
270
ns
345
ns
48
ns
69
ns
46
ns
60
ns
225
ns
300
ns
45
ns
60
ns
39
ns
53
ns
225
ns
45
ns
39
ns
tS
Minimum Setup Time
2.0V
4.5V
50
60
9
13
75
ns
15
ns
6.0V
9
11
13
ns
tH
Minimum Hold Time
2.0V
4.5V
5
30
5
5
5
ns
5
ns
6.0V
5
5
5
ns
tW
Minimum Pulse Width
2.0V
30
80
100
4.5V
9
16
20
120
ns
24
ns
6.0V
8
14
18
20
ns
tTHL, tTLH Maximum Output Rise
and Fall Time
CL 50 pF
2.0V
25
60
75
4.5V
7
12
15
90
ns
18
ns
6.0V
6
10
13
15
ns
tr, tf
Maximum Input Rise and
Fall Time, Clock
2.0V
4.5V
1000
500
1000
500
1000
ns
500
ns
6.0V
400
400
400
ns
CPD
Power Dissipation
(per flip-flop)
Capacitance (Note 5)
OC VCC
30
pF
OC GND
50
pF
CIN
Maximum Input Capacitance
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD CPD VCC2f  ICC VCC, and the no load dynamic current consumption,
IS CPD VCC f  ICC.
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