MAX147ACAP(2001) Просмотр технического описания (PDF) - Maxim Integrated

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MAX147ACAP
(Rev.:2001)

+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

______________________________________________________________Pin Description

PIN

NAME

FUNCTION

1–8

CH0–CH7 Sampling Analog Inputs

9

COM

Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be

stable to ±0.5LSB.

Three-Level Shutdown Input. Pulling SHDN low shuts the MAX146/MAX147 down; otherwise, they are

10

SHDN

fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode.

Letting SHDN float puts the reference-buffer amplifier in external compensation mode.

Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.

11

VREF

In internal reference mode (MAX146 only), the reference buffer provides a 2.500V nominal output,

externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling

REFADJ to VDD.

12

REFADJ

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.

13

AGND

Analog Ground

14

DGND

Digital Ground

15

DOUT

Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX146/MAX147 begin the

16

SSTRB

A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses

high for one clock period before the MSB decision. High impedance when CS is high (external clock

mode).

17

DIN

Serial Data Input. Data is clocked in at SCLK’s rising edge.

18

CS

Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is

high impedance.

19

SCLK

Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60%.)

20

VDD

Positive Supply Voltage

VDD

DOUT

6kΩ

DOUT

6kΩ

DGND

CLOAD

50pF

CLOAD

50pF

DGND

a) High-Z to VOH and VOL to VOH

b) High-Z to VOL and VOH to VOL

Figure 1. Load Circuits for Enable Time

DOUT

6kΩ

DGND

VDD

6kΩ

DOUT

CLOAD

50pF

CLOAD

50pF

DGND

a) VOH to High-Z

b) VOL to High-Z

Figure 2. Load Circuits for Disable Time

8 _______________________________________________________________________________________

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