MAX147ACAP(2001) Просмотр технического описания (PDF) - Maxim Integrated

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MAX147ACAP
(Rev.:2001)

+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

TIMING CHARACTERISTICS

(VDD = +2.7V to +3.6V (MAX146); VDD = +2.7V to +5.25V (MAX147); TA = TMIN to TMAX; unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP

Acquisition Time

tACQ

1.5

DIN to SCLK Setup

tDS

100

DIN to SCLK Hold

tDH

0

MAX14_ _C/E

20

SCLK Fall to Output Data Valid

tDO Figure 1

FMigAuXr1e41_ _M

20

CS Fall to Output Enable

tDV Figure 1

CS Rise to Output Disable

tTR Figure 2

CS to SCLK Rise Setup

tCSS

100

CS to SCLK Rise Hold

tCSH

0

SCLK Pulse Width High

tCH

200

SCLK Pulse Width Low

tCL

200

SCLK Fall to SSTRB

CS Fall to SSTRB Output Enable

CS Rise to SSTRB Output Disable

tSSTRB

tSDV

tSTR

Figure 1

External clock mode only, Figure 1

External clock mode only, Figure 2

SSTRB Rise to SCLK Rise

tSCK Internal clock mode only (Note 9)

0

MAX

200

240

240

240

240

240

240

UNITS

µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.5V), offset nulled.

Note 4: Ground “on” channel; sine wave applied to all “off” channels.

Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6: The common-mode range for the analog inputs is from AGND to VDD.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.

Note 9: Guaranteed by design. Not subject to production testing.

| | Note 10: Measured as VFS(2.7V) - VFS(VDD, MAX) .

Typical Operating Characteristics

(VDD = 3.0V, VREF = 2.5V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)

0.5

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

0

INTEGRAL NONLINEARITY

vs. CODE

1024

2048

3072

4096

CODE

INTEGRAL NONLINEARITY

vs. SUPPLY VOLTAGE

0.50

0.45

0.40

MAX146

0.35

0.30

0.25

0.20

MAX147

0.15

0.10

0.05

0

2.25 2.75 3.25 3.75 4.25 4.75 5.25

VDD (V)

INTEGRAL NONLINEARITY

vs. TEMPERATURE

0.50

0.45 VDD = 2.7V

0.40

0.35

0.30

MAX146

0.25

0.20

0.15

MAX147

0.10

0.05

0

-60 -20

20

60 100 140

TEMPERATURE (°C)

_______________________________________________________________________________________ 5

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