LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

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LJSF32JO2

1 INTRODUCTION

This datasheet contains LH28F320BJE-PI-l-L90

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4 and 5 describe the memory

organization and functionality. Section 6 covers electrical

specifications.

1.1 Features

Key enhancements of LH28F320BJE-PTTL90 boot block

Flash memory are:

*Single low voltage operation

*Low power consumption

*Enhanced Suspend Capabilities

*Boot Block Architecture

Please note following:

l VCCvtK has been lowered to l.OV to support 2.7V-

3.6V block erase, full chip erase, word/byte write and

lock-bit configuration operations. The V,, voltage

transitions to GND is recommended for designs that

switch V,,, off during read operation.

1.2 Product Overview

The LH28F320BJE-PTTL90 is a high-performance 32M-

Iit Boot Block Flash memory organized as 2M-word of 16

)its or 4M-byte of 8 bits. The 2M-word/4M-byte of data is

u-ranged in two 4K-word/8K-byte boot blocks, six 4K-

vord/8K-byte parameter blocks and sixty-three 32K-

vord/64K-byte main blocks which are individually

:rasable, lockable and unlockable in-system. The memory

nap is shown in Figure 3.

The dedicated Vccw pin gives complete data protection

vhen Vccw<V,m,.

, Command User Interface (CUI) serves as the interface

etween the system processor and internal operation of the

evice. A valid command sequence written to the CUI

vitiates device automation. An internal Write State

lachine (WSM) automatically executes the algorithms

Id timings necessary for block erase. full chip erase.

,ord/byte write and lock-bit configuration operations.

A block erase operation erases one of the device’s 32K

word/64K-byte blocks typically within 1.2s (3V V,,. 3\

Vccw), 4K-word/8K-byte blocks typically within 0.6s (3\

V,,. 3V Vccw) independent of other blocks. Each block

can be independently erased minimum 100.000 times

Block erase suspend mode allows system software tc

suspend block erase to read or write data from any other

block.

Writing memory data is performed in word/byu

increments of the device’s 32K-word blocks typically

within 33~s (3V V,,. 3V V,,,), 6JK-byte block!

typically within 31ps (3V V,,. 3V Vccw). 4K-wore

blocks typically within 36~s (3V V,,. 3V Vccw). 8K-

byte blocks typically within 32~s (3V V,,. 3V Vccw).

‘I Word/byte write suspend mode enables the system to reac

data or execute code from any other flash memory array

location.

Individual block locking uses a combination of bits

seventy-one block lock-bits, a permanent lock-bit ant

WP# pin. to lock and unlock blocks. Block lock-bits gate

block erase, full chip erase and word/byte write

operations. while the permanent lock-bit gates block lock-

bit modification and locked block alternation. Lock-bil

configuration operations (Set Block Lock-Bit, Set

Permanent Lock-Bit and Clear Block Lock-Bits

commands) set and cleared lock-bits.

The status register indicates when the WSM’s block erase.

full chip erase, word/byte write or lock-bit configuration

operation is finished.

The RY/BY# output gives an additional indicator of WSM

activity by providing both a hardware signal of status

(versus software polling) and status masking (interrupt

masking for background block erase, for example). Status

polling using RYiBY# minimizes both CPU overhead and

system power consumption. When low, RY/J3Y# indicates

that the WSM is performing a block erase, full chip erase.

word/byte write or lock-bit configuration. RY/BY#-high 2

indicates that the WSM is ready for a new command.

block erase is suspended (and word/byte write is

inactive), word/byte write is suspended, or the device is in

reset mode.

Rev. 1.25

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