LH28F320BJE-PTTL90 Просмотр технического описания (PDF) - Sharp Electronics

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LH28F320BJE-PTTL90

Flash Memory 32M (2M × 16/4M × 8)

Sharp Electronics 

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2 PRINCIPLES OF OPERATION

The LH28F320BIEPTTL90 Flash memory includes an

on-chip WSIM to manage block erase, full chip erase,

word/byte write and lock-bit configuration functions. It

allows for: fixed power supplies during block erase. full

chip erase, word/byte write and lock-bit configuration, and

minimal processor overhead with RAM-like interface

timings.

After initial device power-up or return from reset mode

(see section 3 Bus Operations). the device defaults to read

array mode. Manipulation of external memory control pins

allow array read, standby and output disable operations.

Status register and identifier codes can be accessed

through the CUI independent of the V,, voltage. High

voltage on V,, enables successful block erase, full chip

erase, word/byte write and lock-bit configurations. All

functions associated with altering memory contents-block

erase, full chip erase, word/byte write. lock-bit

zonfigurationt status and identifier codes-are accessed via

he CUI and verified through the status register.

Commands are written using standard microprocessor

write timings. The CUI contents serve as input to the

WSM, which controls the block erase, full chip erase,

word/byte write and lock-bit configuration. The internal

Algorithms are regulated by the WSM. including pulse

.epetition, internal verification and margining of data.

iddresses and data are internally latched during write

:ycles. Writing the appropriate command outputs array

lata, accesses the identifier codes or outputs status register

iata.

Interface software that initiates and polls progress of block

erase, full chip erase, word/byte write and lock-bit

configuration can be stored in any block. This code is

copied to and executed from system RAM during flash

memory updates. After successful completion, reads are

again possible via the Read Array command. Block erase

suspend allows system software to suspend a block erase

to read/write data from/to blocks other than that which is

suspend. Word/byte write suspend allows system software

to suspend a word/byte write to read data from any other

flash memory array location.

2.1 Data Protection

When V,&VccwLK.

memory contents cannot be

altered. The CUI, with two-step block erase, full chip

erase, word/byte write or lock-bit configuration command

sequences, provides protection from unwanted operations

even when high voltage is applied to Vccw. All write

functions are disabled when V,, is below the write

lockout voltage V,,, or when RP# is at V,. The device’s

block locking capability provides additional protection

from inadvertent code or data alteration by gating block

erase. full chip erase and word/byte write operations.

Refer to Table 5 for write protection alternatives.

Rev. 1.25

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