ISP1161A Просмотр технического описания (PDF) - Philips Electronics
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ISP1161A Datasheet PDF : 134 Pages
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Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
9397 750 13962
Product data
Table 2: Pin description for LQFP64 …continued
Symbol[1]
Pin Type Description
D6
6
I/O
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D7
7
I/O
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
8
-
digital ground
D8
9
I/O
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D9
10 I/O
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D10
11 I/O
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D11
12 I/O
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D12
13 I/O
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D13
14 I/O
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
15 -
digital ground
D14
16 I/O
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D15
17 I/O
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
18 -
digital ground
Vhold1
19 -
voltage holding pin; internally connected to the Vreg(3.3) and
Vhold2 pins. When VCC is connected to 5 V, this pin will
output 3.3 V, hence do not connect it to 5 V. When VCC is
connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
n.c.
20 -
no connection
CS
21 I
chip select input
RD
22 I
read strobe input
WR
23 I
write strobe input
Vhold2
24 -
voltage holding pin; internally connected to the Vreg(3.3) and
Vhold1 pins. When VCC is connected to 5 V, this pin will
output 3.3 V, hence do not connect it to 5 V. When VCC is
connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
DREQ1
25 O
HC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1161A wants to start a
DMA transfer; see Section 10.4.1
DREQ2
26 O
DC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1161A wants to start a
DMA transfer; see Section 13.1.4
DACK1
27 I
HC DMA acknowledge input; when not in use, this pin must
be connected to VCC via an external 10 kΩ resistor
Rev. 03 — 23 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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